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From: Ivan Vecera <ivecera@redhat.com>
To: Jiri Pirko <jiri@resnulli.us>, Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: netdev@vger.kernel.org,
	Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Prathosh Satish <Prathosh.Satish@microchip.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Simon Horman <horms@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
	Jason Gunthorpe <jgg@ziepe.ca>,
	Shannon Nelson <shannon.nelson@amd.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org, Michal Schmidt <mschmidt@redhat.com>,
	Petr Oros <poros@redhat.com>
Subject: Re: [PATCH net-next v12 07/14] dpll: zl3073x: Add clock_id field
Date: Thu, 3 Jul 2025 12:45:31 +0200	[thread overview]
Message-ID: <bacab4b5-5c7f-4ece-9ca9-08723ec91aec@redhat.com> (raw)
In-Reply-To: <pfkr62fp4jr2bts3ektfwn4or36lqdsdqfsntryubr5oawx7kv@adqwk2qoflhu>



On 03. 07. 25 12:09 odp., Jiri Pirko wrote:
> Wed, Jul 02, 2025 at 04:51:47PM +0200, ivecera@redhat.com wrote:
>> On 02. 07. 25 2:01 odp., Jiri Pirko wrote:
>>> Wed, Jul 02, 2025 at 01:43:38PM +0200, ivecera@redhat.com wrote:
>>>>
>>>> On 02. 07. 25 12:31 odp., Jiri Pirko wrote:
>>>>> Sun, Jun 29, 2025 at 09:10:42PM +0200, ivecera@redhat.com wrote:
>>>>>> Add .clock_id to zl3073x_dev structure that will be used by later
>>>>>> commits introducing DPLL feature. The clock ID is required for DPLL
>>>>>> device registration.
>>>>>>
>>>>>> To generate this ID, use chip ID read during device initialization.
>>>>>> In case where multiple zl3073x based chips are present, the chip ID
>>>>>> is shifted and lower bits are filled by an unique value - using
>>>>>> the I2C device address for I2C connections and the chip-select value
>>>>>> for SPI connections.
>>>>>
>>>>> You say that multiple chips may have the same chip ID? How is that
>>>>> possible? Isn't it supposed to be unique?
>>>>> I understand clock ID to be invariant regardless where you plug your
>>>>> device. When you construct it from i2c address, sounds wrong.
>>>>
>>>> The chip id is not like serial number but it is like device id under
>>>> PCI. So if you will have multiple chips with this chip id you have to
>>>> distinguish somehow between them, this is the reason why I2C address
>>>> is added into the final value.
>>>>
>>>> Anyway this device does not have any attribute that corresponds to
>>>> clock id (as per our previous discussion) and it will be better to NOT
>>>> require clock id from DPLL core side.
>>>
>>> Yes, better not to require it comparing to having it wrong.
>>
>> It looks that using clock_id==0 is safe from DPLL API point of view.
>> The problem is if you will have multiple zl3073x based chips because
>> the driver would call dpll_device_get(0 /* clock_id */, channel, module)
>>
>> For 1st chip (e.g. 2 channel) the driver will call:
>> dpll_device_get(0, 0, module);
>> dpll_device_get(0, 1, module);
>>
>> and for the second the same that is wrong. The clock_id would help to
>> distinguish between them.
>>
>> Wouldn't it be better to use a random number for clock_id from the
>> driver?
> 
> I take my suggestion to not require it back, does not make sense.
> 
> Clock id actually has a reason to exist from UAPI perspective. Checkout
> dpll_device_find_from_nlattr(). The user passes CLOCK_ID attr (among
> others) to obtain device by DPLL_CMD_DEVICE_ID_GET command. He expects
> to get a result back from kernel regardless where the device is plugged
> and across the reboots/rebinds.
> 
> Clock id should be properly filled with static and device specific
> value. If your chip can't be queried for it, I'm sure the embedded world
> has a solution for such cases. It's similar to MAC of a NIC device.

Yes, there are such cases and for such devices 'mac-address' property
can be specified in the device tree.

For our case I could extend the dpll device schema to include 'clock-id'
or 'dpll-clock-id' 64bit property to allow specify clock ID for the
devices that are unable to query this information from the hardware.

Krzysztof, WDYT about it?

Thanks,
Ivan


  reply	other threads:[~2025-07-03 10:45 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-29 19:10 [PATCH net-next v12 00/14] Add Microchip ZL3073x support (part 1) Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 01/14] dt-bindings: dpll: Add DPLL device and pin Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 02/14] dt-bindings: dpll: Add support for Microchip Azurite chip family Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 03/14] dpll: Add basic Microchip ZL3073x support Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 04/14] dpll: zl3073x: Add support for devlink device info Ivan Vecera
2025-07-02 10:25   ` Jiri Pirko
2025-07-02 11:38     ` Ivan Vecera
2025-07-02 11:41       ` Jiri Pirko
2025-07-02 11:52         ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 05/14] dpll: zl3073x: Protect operations requiring multiple register accesses Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 06/14] dpll: zl3073x: Fetch invariants during probe Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 07/14] dpll: zl3073x: Add clock_id field Ivan Vecera
2025-07-02 10:31   ` Jiri Pirko
2025-07-02 11:43     ` Ivan Vecera
2025-07-02 12:01       ` Jiri Pirko
2025-07-02 14:51         ` Ivan Vecera
2025-07-03 10:09           ` Jiri Pirko
2025-07-03 10:45             ` Ivan Vecera [this message]
2025-06-29 19:10 ` [PATCH net-next v12 08/14] dpll: zl3073x: Read DPLL types and pin properties from system firmware Ivan Vecera
2025-07-02 10:41   ` Jiri Pirko
2025-07-02 11:47     ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 09/14] dpll: zl3073x: Register DPLL devices and pins Ivan Vecera
2025-07-02 10:57   ` Jiri Pirko
2025-07-02 11:49     ` Ivan Vecera
2025-07-02 12:02       ` Jiri Pirko
2025-07-02 12:16         ` Ivan Vecera
2025-07-02 14:12           ` Jiri Pirko
2025-06-29 19:10 ` [PATCH net-next v12 10/14] dpll: zl3073x: Implement input pin selection in manual mode Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 11/14] dpll: zl3073x: Add support to get/set priority on input pins Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 12/14] dpll: zl3073x: Implement input pin state setting in automatic mode Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 13/14] dpll: zl3073x: Add support to get/set frequency on input pins Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 14/14] dpll: zl3073x: Add support to get/set frequency on output pins Ivan Vecera

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