From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAE5333A9E1; Sat, 22 Aug 2026 07:39:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384343; cv=none; b=bkirich2ja13iSm10tCC9U01tcMF83WuhLRO4o5boIYhVExIkL9nG5LLZk2yJfoNsnWfZZKetj+8B3mDkyng8HQWNzctXtZfZJ69QeTH4ENqYSCXMi3zGpHEnJKHL1T9VBoQPKpijZc4LKoK6x7WU5FsfR3pO3ueqVpw4kdwGVc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384343; c=relaxed/simple; bh=20a6T6gfT4W5qmnR0IrhYYQg42UJNxpelFM+vKlIzts=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Z6h9zTHKxz9GkPK8xzBMBI0EQLehqjfVRlwfd0g4T3mool/8M/ffEZY9tz1NbVnuEhTqhUhNxxSfm6oOGPKNZ9D7bEQd2l+oyKfTpNjxRo4+GOJMzYb0yPONaKyvdYLiE8UmcQbOPGb4S86T3NVw8WsIJFq3dAPf0t7Iz7wmaWA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b1glk2k4; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b1glk2k4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A530C1F000E9; Sat, 22 Aug 2026 07:38:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787384341; bh=yxr1RTUyhpEzexigkTUOYj2YkjiALBk7cwuLfHLoWhw=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=b1glk2k40qB8dX5lLhDAvudDvtFkuzSyLzo1JY5Q8j0hSsZJ3NJ2LML6TlRZ5GswT 7Ekgb/1vALB6v3GCqYm4j6jQk3xUYf9F1ru/ECBWGYj24rF2szfwIvvh9ev7wUZjb9 CslsXIxNbyT5Oopd28Tfpy46F4KWB3qThbkelu9NZE5f0dbPaaXos3RLypkCxgFJOf hK031J0UNOUjGRzBOftKd1DgmvSvekyVRkObuLtwrbDNRHJUh2QOQHxcMcdvKKNnhO GGb6r7Ew0Wjw9raX13M8l4WMm+xAdU/Y2JbxwTsQpWSUk/E/l1eswlVQ/7bExIHYhm bIEnRjhLtaSXg== Message-ID: Date: Sat, 22 Aug 2026 09:38:51 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI for RZ/G2M v3.0 To: Ayman Chaudhry , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Brian Masney , Jerome Brunet , Ulf Hansson Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , Fabrizio Castro , Lad Prabhakar References: <20260821150408.73829-1-ayman.chaudhry.kc@renesas.com> <20260821150408.73829-9-ayman.chaudhry.kc@renesas.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 21/08/2026 17:03, Ayman Chaudhry wrote: > Add initial Device Tree Source Include (DTSI) file for the Renesas > RZ/G2M v3.0 (a.k.a. R8A774A3) SoC with basic support. > > Signed-off-by: Ayman Chaudhry > --- > arch/arm64/boot/dts/renesas/r8a774a3.dtsi | 302 ++++++++++++++++++++++ > 1 file changed, 302 insertions(+) > create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3.dtsi > > diff --git a/arch/arm64/boot/dts/renesas/r8a774a3.dtsi b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi > new file mode 100644 > index 000000000000..f60a31612b39 > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi > @@ -0,0 +1,302 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the r8a774a3 SoC > + * > + * Copyright (C) 2026 Renesas Electronics Corp. > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "renesas,r8a774a3"; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + > + cluster0_opp: opp-table-0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + }; > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + }; > + opp-1500000000 { > + opp-hz = /bits/ 64 <1500000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + opp-suspend; > + }; > + }; > + > + cluster1_opp: opp-table-1 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + }; > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + }; > + opp-1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&a57_0>; > + }; > + core1 { > + cpu = <&a57_1>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&a53_0>; > + }; > + core1 { > + cpu = <&a53_1>; > + }; > + core2 { > + cpu = <&a53_2>; > + }; > + core3 { > + cpu = <&a53_3>; > + }; > + }; > + }; > + > + a57_0: cpu@0 { > + compatible = "arm,cortex-a57"; > + reg = <0x0>; > + device_type = "cpu"; > + power-domains = <&sysc R8A774A3_PD_CA57_CPU0>; > + next-level-cache = <&L2_CA57>; > + enable-method = "psci"; > + dynamic-power-coefficient = <854>; > + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>; > + operating-points-v2 = <&cluster0_opp>; > + capacity-dmips-mhz = <1024>; > + }; > + > + a57_1: cpu@1 { > + compatible = "arm,cortex-a57"; > + reg = <0x1>; > + device_type = "cpu"; > + power-domains = <&sysc R8A774A3_PD_CA57_CPU1>; > + next-level-cache = <&L2_CA57>; > + enable-method = "psci"; > + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>; > + operating-points-v2 = <&cluster0_opp>; > + capacity-dmips-mhz = <1024>; > + }; > + > + a53_0: cpu@100 { > + compatible = "arm,cortex-a53"; > + reg = <0x100>; > + device_type = "cpu"; > + power-domains = <&sysc R8A774A3_PD_CA53_CPU0>; > + next-level-cache = <&L2_CA53>; > + enable-method = "psci"; > + dynamic-power-coefficient = <277>; > + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>; > + operating-points-v2 = <&cluster1_opp>; > + capacity-dmips-mhz = <560>; > + }; > + > + a53_1: cpu@101 { > + compatible = "arm,cortex-a53"; > + reg = <0x101>; > + device_type = "cpu"; > + power-domains = <&sysc R8A774A3_PD_CA53_CPU1>; > + next-level-cache = <&L2_CA53>; > + enable-method = "psci"; > + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>; > + operating-points-v2 = <&cluster1_opp>; > + capacity-dmips-mhz = <560>; > + }; > + > + a53_2: cpu@102 { > + compatible = "arm,cortex-a53"; > + reg = <0x102>; > + device_type = "cpu"; > + power-domains = <&sysc R8A774A3_PD_CA53_CPU2>; > + next-level-cache = <&L2_CA53>; > + enable-method = "psci"; > + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>; > + operating-points-v2 = <&cluster1_opp>; > + capacity-dmips-mhz = <560>; > + }; > + > + a53_3: cpu@103 { > + compatible = "arm,cortex-a53"; > + reg = <0x103>; > + device_type = "cpu"; > + power-domains = <&sysc R8A774A3_PD_CA53_CPU3>; > + next-level-cache = <&L2_CA53>; > + enable-method = "psci"; > + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>; > + operating-points-v2 = <&cluster1_opp>; > + capacity-dmips-mhz = <560>; > + }; > + > + L2_CA57: cache-controller-0 { > + compatible = "cache"; > + power-domains = <&sysc R8A774A3_PD_CA57_SCU>; > + cache-unified; > + cache-level = <2>; > + }; > + > + L2_CA53: cache-controller-1 { > + compatible = "cache"; > + power-domains = <&sysc R8A774A3_PD_CA53_SCU>; > + cache-unified; > + cache-level = <2>; > + }; > + }; > + > + extal_clk: extal { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + bootph-all; > + }; > + > + extalr_clk: extalr { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + bootph-all; > + }; > + > + pmu_a53 { Please, do not send us downstream code. It looks awfully like one. It's long time fixed in all upstream platforms. Also, this causes now warnings. Best regards, Krzysztof