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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>,
	Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC v4 2/9] dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros
Date: Tue, 16 Jun 2026 16:07:27 +0200	[thread overview]
Message-ID: <bb3dd1d0-af41-4ecf-b23a-3800aa5414ce@oss.qualcomm.com> (raw)
In-Reply-To: <20260518-link_mode_0519-v4-2-269cd73cc5d1@oss.qualcomm.com>

On 5/19/26 7:47 AM, Qiang Yu wrote:
> Add two sets of constants to phy-qcom-qmp.h to support upcoming multiple
> link mode QMP PHY:
> 
> - QMP_PHY_SELECTOR_0 / QMP_PHY_SELECTOR_1: generic logical PHY index
>   values for QMP providers that expose multiple PHY instances under a
>   single DT node (i.e. #phy-cells = <1>).
> 
> - QMP_PCIE_GLYMUR_MODE_X8 / QMP_PCIE_GLYMUR_MODE_X4X4: link-mode
>   values for the Glymur Gen5x8 PCIe PHY "qcom,link-mode" syscon property,
>   selecting between the x8 single-PHY and x4+x4 dual-PHY topologies.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
>  include/dt-bindings/phy/phy-qcom-qmp.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h
> index 6b43ea9e0051..befa76f8392f 100644
> --- a/include/dt-bindings/phy/phy-qcom-qmp.h
> +++ b/include/dt-bindings/phy/phy-qcom-qmp.h
> @@ -21,4 +21,12 @@
>  #define QMP_PCIE_PIPE_CLK		0
>  #define QMP_PCIE_PHY_AUX_CLK		1
>  
> +/* Generic QMP logical PHY selectors */
> +#define QMP_PHY_SELECTOR_0		0
> +#define QMP_PHY_SELECTOR_1		1

Is this for the second phy cell? FWIW I think it's fine to use raw
numbers as they're just indices (i.e. "nth bifurcated phy") anyway

Konrad

  reply	other threads:[~2026-06-16 14:07 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-19  5:47 [PATCH RFC v4 0/9] phy: qcom: qmp-pcie: Add link-mode based support for Glymur Gen5x8 PHY Qiang Yu
2026-05-19  5:47 ` [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible Qiang Yu
2026-06-16 14:03   ` Konrad Dybcio
2026-06-29  5:14     ` Qiang Yu
2026-06-29  9:20       ` Konrad Dybcio
2026-05-19  5:47 ` [PATCH RFC v4 2/9] dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros Qiang Yu
2026-06-16 14:07   ` Konrad Dybcio [this message]
2026-06-29  5:18     ` Qiang Yu
2026-06-29  9:21       ` Konrad Dybcio
2026-05-19  5:47 ` [PATCH RFC v4 3/9] phy: qcom: qmp-pcie: Add multiple power-domains support Qiang Yu
2026-05-19  5:47 ` [PATCH RFC v4 4/9] phy: qcom: qmp-pcie: Support multiple nocsr resets Qiang Yu
2026-05-19  5:47 ` [PATCH RFC v4 5/9] phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers Qiang Yu
2026-05-20 16:25   ` Dmitry Baryshkov
2026-05-22 10:57     ` Manivannan Sadhasivam
2026-05-28 13:15       ` Qiang Yu
2026-05-28 13:48       ` Dmitry Baryshkov
2026-05-29  7:02         ` Qiang Yu
2026-06-16 14:05           ` Konrad Dybcio
2026-06-29  5:56             ` Qiang Yu
2026-06-29  9:21               ` Konrad Dybcio
2026-05-19  5:47 ` [PATCH RFC v4 6/9] phy: qcom: qmp-pcie: Add clock and reset lists for secondary PHY selector Qiang Yu
2026-05-19  5:47 ` [PATCH RFC v4 7/9] phy: qcom: qmp-pcie: Add link-mode multi-PHY probe infrastructure Qiang Yu
2026-05-19  5:47 ` [PATCH RFC v4 8/9] phy: qcom: qmp-pcie: Add Glymur Gen5x8 PHY config and match data Qiang Yu
2026-05-19  5:47 ` [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY Qiang Yu
2026-06-17 11:19   ` Konrad Dybcio
2026-06-29  5:05     ` Qiang Yu
2026-06-29  9:20       ` Konrad Dybcio

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