From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 280AE3A1A5C; Mon, 16 Mar 2026 16:44:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773679448; cv=none; b=OG96BnlmikS1adSUVeGO7Sffp2/HrKkpxIV1T0DjamOmdwh7VcOTiIQg5c5ZNnR87dOLEH1o1645/YIUCWaMpVhVuBh8th50bEl5CeEetkRyz9LTh0B0Du1KTqEDirUSxBemZhDWyLF28zcS3GQWeFlE7ICVAfJMW6kAy+5DrbM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773679448; c=relaxed/simple; bh=UJiJGdnIbo8YhWP9a8898EeByRFPPoe9G04ORqwYyao=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=UP/L1vUH39Tnry5OKU59Zwf3likw2aCWpy8kO3uHelyjXc1iBM6Us4p/SpP/qr9kp9RvfHW7ORKlq09KqsZUgxB9h9S9T/RC3/iWVuyeh++rA3/ZjxB465npqPipAHPm8bEia7GeyYeP0YJ8nkX9zMneqdf1DMwm61UYLbO+Y0o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kNq3N96w; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kNq3N96w" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97EFDC19421; Mon, 16 Mar 2026 16:44:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773679448; bh=UJiJGdnIbo8YhWP9a8898EeByRFPPoe9G04ORqwYyao=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=kNq3N96w1Uyh9BHrPZnStKE3rWXHfkL/gk6W/wkus/0NBFRkv0EO/+10w1ZnP4V5P RGl2dfpJ6Ee0c7aV0BiBoXX1Qiu1rR1s5f3QQ3CxytQrnivU1ip1kH79vZDcgmZccc PvLfb3s1iH2p4F6Tvr6pLL5Tm0jgF8RebY2LCkkYWaNie21VhThcOcEIQj6/rmL7vp eK07/QA6xGM6up9uwIUbDIgjBkzFt9ltdecOzTJ68omLfVjjHXrOFU/LJZZu6KSe6h XrPpzP61JJNXwX5O9PwbtHbp7BM9uFLQ6VuNtL17KXUz/Z4WHL2cbMBWORm4VBPBzL 764nAuua2hjPQ== Message-ID: Date: Mon, 16 Mar 2026 17:44:02 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints To: Swamil Jain Cc: jyri.sarha@iki.fi, tomi.valkeinen@ideasonboard.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devarsht@ti.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, praneeth@ti.com, vigneshr@ti.com References: <20260129150601.185882-1-s-jain1@ti.com> <20260205-spectral-dramatic-jellyfish-cec4e2@quoll> <4b554339-95e1-4980-8899-57ba637ba80c@ti.com> <7b3660cf-cc5a-47d6-9cc8-362544cfdb37@ti.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 16/03/2026 13:36, Swamil Jain wrote: >>     description: >>       Addresses to each DSS memory region described in the SoC's TRM. >>     oneOf: >>       - items: >>           - description: common DSS register area >>           - description: VIDL1 light video plane >>           - description: VID video plane >>           - description: OVR1 overlay manager for vp1 >>           - description: OVR2 overlay manager for vp2 >>           - description: VP1 video port 1 >>           - description: VP2 video port 2 >>           - description: common1 DSS register area >>       - items: >>           - description: common DSS register area >>           - description: VIDL1 light video plane >>           - description: OVR1 overlay manager for vp1 >>           - description: VP1 video port 1 >>           - description: common1 DSS register area >> >> .....(Similarly for reg-names, clocks, clock-names,...) >> >> allOf: >>   - if: >>       properties: >>         compatible: >>           contains: >>             const: ti,am62l-dss >>     then: >>       properties: >>         clock-names: >>           maxItems: 2 >>         clocks: >>           maxItems: 2 >>         reg: >>           maxItems: 5 >>     else: >>       properties: >>         clock-names: >>           minItems: 3 >>         clocks: >>           minItems: 3 >>         reg: >>           minItems: 8 >> >> ``` >> >> Could you please confirm on this? If there is no common part of each list, then this looks correct. Other way would be the example I wrote ~2 hours ago on DT IRC (different patchset) - so the qcom,ufs way. It depends how readable is the final schema. > > Hi Krzysztof, > > Gentle ping, could you please confirm on the above design? If you do not hear from me or other reviewer for some time after asking "shall I do like that", just send next version implementing what you think should be done and mentioning in changelog, that this is how you address reviewers feedback. Best regards, Krzysztof