[PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[Swamil Jain]

The AM62L DSS [1] support incorrectly used the same register and
clock constraints as AM65x, but AM62L has a single video port.

Fix this by adding conditional constraints that properly define the
register regions and clocks for AM62L DSS (single video port) versus
other AM65x variants (dual video port).

[1]: Section 12.7 (Display Subsystem and Peripherals)
Link : https://www.ti.com/lit/pdf/sprujb4

Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS")
Cc: stable@vger.kernel.org

Signed-off-by: Swamil Jain <s-jain1@ti.com>
---
Changelog:
v1->v2:
- Remove oneOf from top level constraints, it makes bindings redundant
- Remove minItems from top level constraints
- "dma-coherent" property shouldn't be changed in v1 itself
- Add description for reg-names, clock and clock-names
- Add constraints specific to AM62L and for other SoCs within allOf
  check

Link to v1:
https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/
---
 .../bindings/display/ti/ti,am65x-dss.yaml     | 93 +++++++++++++------
 1 file changed, 67 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
index 38fcee91211e..dbc9d754cf9e 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -36,38 +36,18 @@ properties:
   reg:
     description:
       Addresses to each DSS memory region described in the SoC's TRM.
-    items:
-      - description: common DSS register area
-      - description: VIDL1 light video plane
-      - description: VID video plane
-      - description: OVR1 overlay manager for vp1
-      - description: OVR2 overlay manager for vp2
-      - description: VP1 video port 1
-      - description: VP2 video port 2
-      - description: common1 DSS register area
 
   reg-names:
-    items:
-      - const: common
-      - const: vidl1
-      - const: vid
-      - const: ovr1
-      - const: ovr2
-      - const: vp1
-      - const: vp2
-      - const: common1
+    description:
+      Names for each memory region described in the reg property.
 
   clocks:
-    items:
-      - description: fck DSS functional clock
-      - description: vp1 Video Port 1 pixel clock
-      - description: vp2 Video Port 2 pixel clock
+    description:
+      Clocks used by the DSS. The number and order depends on the SoC variant.
 
   clock-names:
-    items:
-      - const: fck
-      - const: vp1
-      - const: vp2
+    description:
+      Names for each clock described in the clocks property. The number and order depends on the SoC variant.
 
   assigned-clocks:
     minItems: 1
@@ -195,6 +175,67 @@ allOf:
             port@0:
               properties:
                 endpoint@1: false
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,am62l-dss
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: fck
+            - const: vp1
+        clocks:
+          items:
+            - description: fck DSS functional clock
+            - description: vp1 Video Port 1 pixel clock
+        reg:
+          items:
+            - description: common DSS register area
+            - description: VIDL1 light video plane
+            - description: OVR1 overlay manager for vp1
+            - description: VP1 video port 1
+            - description: common1 DSS register area
+        reg-names:
+          items:
+            - const: common
+            - const: vidl1
+            - const: ovr1
+            - const: vp1
+            - const: common1
+    else:
+      properties:
+        clock-names:
+          items:
+            - const: fck
+            - const: vp1
+            - const: vp2
+        clocks:
+          items:
+            - description: fck DSS functional clock
+            - description: vp1 Video Port 1 pixel clock
+            - description: vp2 Video Port 2 pixel clock
+        reg:
+          items:
+            - description: common DSS register area
+            - description: VIDL1 light video plane
+            - description: VID video plane
+            - description: OVR1 overlay manager for vp1
+            - description: OVR2 overlay manager for vp2
+            - description: VP1 video port 1
+            - description: VP2 video port 2
+            - description: common1 DSS register area
+        reg-names:
+          items:
+            - const: common
+            - const: vidl1
+            - const: vid
+            - const: ovr1
+            - const: ovr2
+            - const: vp1
+            - const: vp2
+            - const: common1
 
 required:
   - compatible

Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[Krzysztof Kozlowski]

On Thu, Jan 29, 2026 at 08:36:01PM +0530, Swamil Jain wrote:
> The AM62L DSS [1] support incorrectly used the same register and
> clock constraints as AM65x, but AM62L has a single video port.
> 
> Fix this by adding conditional constraints that properly define the
> register regions and clocks for AM62L DSS (single video port) versus
> other AM65x variants (dual video port).
> 
> [1]: Section 12.7 (Display Subsystem and Peripherals)
> Link : https://www.ti.com/lit/pdf/sprujb4
> 
> Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS")
> Cc: stable@vger.kernel.org
> 

There are never blank lines between tags.

> Signed-off-by: Swamil Jain <s-jain1@ti.com>
> ---
> Changelog:
> v1->v2:
> - Remove oneOf from top level constraints, it makes bindings redundant
> - Remove minItems from top level constraints
> - "dma-coherent" property shouldn't be changed in v1 itself
> - Add description for reg-names, clock and clock-names
> - Add constraints specific to AM62L and for other SoCs within allOf
>   check
> 
> Link to v1:
> https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/
> ---
>  .../bindings/display/ti/ti,am65x-dss.yaml     | 93 +++++++++++++------
>  1 file changed, 67 insertions(+), 26 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 38fcee91211e..dbc9d754cf9e 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -36,38 +36,18 @@ properties:
>    reg:
>      description:
>        Addresses to each DSS memory region described in the SoC's TRM.
> -    items:
> -      - description: common DSS register area
> -      - description: VIDL1 light video plane
> -      - description: VID video plane
> -      - description: OVR1 overlay manager for vp1
> -      - description: OVR2 overlay manager for vp2
> -      - description: VP1 video port 1
> -      - description: VP2 video port 2
> -      - description: common1 DSS register area

No, I do not understand this change. We spoke so many times, documented
it, wrotre on presentation slides: broadest constraints are always
defined in top level. TI received this feedback more than once.

Sorry guys, but you are not individual contributors which do it in spare
time. Why the same feedback - already documented - has to be repeated?

Best regards,
Krzysztof

Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[Swamil Jain]

Hi Krzysztof,

On 2/5/26 18:55, Krzysztof Kozlowski wrote:
> On Thu, Jan 29, 2026 at 08:36:01PM +0530, Swamil Jain wrote:
>> The AM62L DSS [1] support incorrectly used the same register and
>> clock constraints as AM65x, but AM62L has a single video port.
>>
>> Fix this by adding conditional constraints that properly define the
>> register regions and clocks for AM62L DSS (single video port) versus
>> other AM65x variants (dual video port).
>>
>> [1]: Section 12.7 (Display Subsystem and Peripherals)
>> Link : https://www.ti.com/lit/pdf/sprujb4
>>
>> Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS")
>> Cc: stable@vger.kernel.org
>>
> 
> There are never blank lines between tags.
> 

Sorry, will fix this.

>> Signed-off-by: Swamil Jain <s-jain1@ti.com>
>> ---
>> Changelog:
>> v1->v2:
>> - Remove oneOf from top level constraints, it makes bindings redundant
>> - Remove minItems from top level constraints
>> - "dma-coherent" property shouldn't be changed in v1 itself
>> - Add description for reg-names, clock and clock-names
>> - Add constraints specific to AM62L and for other SoCs within allOf
>>    check
>>
>> Link to v1:
>> https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/
>> ---
>>   .../bindings/display/ti/ti,am65x-dss.yaml     | 93 +++++++++++++------
>>   1 file changed, 67 insertions(+), 26 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> index 38fcee91211e..dbc9d754cf9e 100644
>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> @@ -36,38 +36,18 @@ properties:
>>     reg:
>>       description:
>>         Addresses to each DSS memory region described in the SoC's TRM.
>> -    items:
>> -      - description: common DSS register area
>> -      - description: VIDL1 light video plane
>> -      - description: VID video plane
>> -      - description: OVR1 overlay manager for vp1
>> -      - description: OVR2 overlay manager for vp2
>> -      - description: VP1 video port 1
>> -      - description: VP2 video port 2
>> -      - description: common1 DSS register area
> 
> No, I do not understand this change. We spoke so many times, documented
> it, wrotre on presentation slides: broadest constraints are always
> defined in top level. TI received this feedback more than once.
> 

There is no superset constraints since am62l register sequence (common, 
vidl1, ovr1, vp1, common1) is different than non-am62l SoCs (common, 
vidl1, vid, ...-> here it is different), so thought to adopt this 
approach where there is if-else block for each SoC and ran this through 
dt-bindings check as well, looking at the replies maybe I misunderstood 
what the suggestion was, reading the reply as I understand below is the 
suggestion:

```
reg:
     description:
       Addresses to each DSS memory region described in the SoC's TRM.
     oneOf:
       - items:
           - description: common DSS register area
           - description: VIDL1 light video plane
           - description: VID video plane
           - description: OVR1 overlay manager for vp1
           - description: OVR2 overlay manager for vp2
           - description: VP1 video port 1
           - description: VP2 video port 2
           - description: common1 DSS register area
       - items:
           - description: common DSS register area
           - description: VIDL1 light video plane
           - description: OVR1 overlay manager for vp1
           - description: VP1 video port 1
           - description: common1 DSS register area

.....(Similarly for reg-names, clocks, clock-names,...)

allOf:
   - if:
       properties:
         compatible:
           contains:
             const: ti,am62l-dss
     then:
       properties:
         clock-names:
           maxItems: 2
         clocks:
           maxItems: 2
         reg:
           maxItems: 5
     else:
       properties:
         clock-names:
           minItems: 3
         clocks:
           minItems: 3
         reg:
           minItems: 8

```

Could you please confirm on this?

Regards,
Swamil.


> Sorry guys, but you are not individual contributors which do it in spare
> time. Why the same feedback - already documented - has to be repeated?
> 
> Best regards,
> Krzysztof
> 
> 

Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[Swamil Jain]

On 2/6/26 19:48, Swamil Jain wrote:
> Hi Krzysztof,
> 
> On 2/5/26 18:55, Krzysztof Kozlowski wrote:
>> On Thu, Jan 29, 2026 at 08:36:01PM +0530, Swamil Jain wrote:
>>> The AM62L DSS [1] support incorrectly used the same register and
>>> clock constraints as AM65x, but AM62L has a single video port.
>>>
>>> Fix this by adding conditional constraints that properly define the
>>> register regions and clocks for AM62L DSS (single video port) versus
>>> other AM65x variants (dual video port).
>>>
>>> [1]: Section 12.7 (Display Subsystem and Peripherals)
>>> Link : https://www.ti.com/lit/pdf/sprujb4
>>>
>>> Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support 
>>> for AM62L DSS")
>>> Cc: stable@vger.kernel.org
>>>
>>
>> There are never blank lines between tags.
>>
> 
> Sorry, will fix this.
> 
>>> Signed-off-by: Swamil Jain <s-jain1@ti.com>
>>> ---
>>> Changelog:
>>> v1->v2:
>>> - Remove oneOf from top level constraints, it makes bindings redundant
>>> - Remove minItems from top level constraints
>>> - "dma-coherent" property shouldn't be changed in v1 itself
>>> - Add description for reg-names, clock and clock-names
>>> - Add constraints specific to AM62L and for other SoCs within allOf
>>>    check
>>>
>>> Link to v1:
>>> https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/
>>> ---
>>>   .../bindings/display/ti/ti,am65x-dss.yaml     | 93 +++++++++++++------
>>>   1 file changed, 67 insertions(+), 26 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x- 
>>> dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x- 
>>> dss.yaml
>>> index 38fcee91211e..dbc9d754cf9e 100644
>>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>>> @@ -36,38 +36,18 @@ properties:
>>>     reg:
>>>       description:
>>>         Addresses to each DSS memory region described in the SoC's TRM.
>>> -    items:
>>> -      - description: common DSS register area
>>> -      - description: VIDL1 light video plane
>>> -      - description: VID video plane
>>> -      - description: OVR1 overlay manager for vp1
>>> -      - description: OVR2 overlay manager for vp2
>>> -      - description: VP1 video port 1
>>> -      - description: VP2 video port 2
>>> -      - description: common1 DSS register area
>>
>> No, I do not understand this change. We spoke so many times, documented
>> it, wrotre on presentation slides: broadest constraints are always
>> defined in top level. TI received this feedback more than once.
>>
> 
> There is no superset constraints since am62l register sequence (common, 
> vidl1, ovr1, vp1, common1) is different than non-am62l SoCs (common, 
> vidl1, vid, ...-> here it is different), so thought to adopt this 
> approach where there is if-else block for each SoC and ran this through 
> dt-bindings check as well, looking at the replies maybe I misunderstood 
> what the suggestion was, reading the reply as I understand below is the 
> suggestion:
> 
> ```
> reg:
>      description:
>        Addresses to each DSS memory region described in the SoC's TRM.
>      oneOf:
>        - items:
>            - description: common DSS register area
>            - description: VIDL1 light video plane
>            - description: VID video plane
>            - description: OVR1 overlay manager for vp1
>            - description: OVR2 overlay manager for vp2
>            - description: VP1 video port 1
>            - description: VP2 video port 2
>            - description: common1 DSS register area
>        - items:
>            - description: common DSS register area
>            - description: VIDL1 light video plane
>            - description: OVR1 overlay manager for vp1
>            - description: VP1 video port 1
>            - description: common1 DSS register area
> 
> .....(Similarly for reg-names, clocks, clock-names,...)
> 
> allOf:
>    - if:
>        properties:
>          compatible:
>            contains:
>              const: ti,am62l-dss
>      then:
>        properties:
>          clock-names:
>            maxItems: 2
>          clocks:
>            maxItems: 2
>          reg:
>            maxItems: 5
>      else:
>        properties:
>          clock-names:
>            minItems: 3
>          clocks:
>            minItems: 3
>          reg:
>            minItems: 8
> 
> ```
> 
> Could you please confirm on this?

Hi Krzysztof,

Gentle ping, could you please confirm on the above design?

Regards,
Swamil.

> 
> Regards,
> Swamil.
> 
> 
>> Sorry guys, but you are not individual contributors which do it in spare
>> time. Why the same feedback - already documented - has to be repeated?
>>
>> Best regards,
>> Krzysztof
>>
>>
> 
> 

Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[Krzysztof Kozlowski]

On 16/03/2026 13:36, Swamil Jain wrote:
>>      description:
>>        Addresses to each DSS memory region described in the SoC's TRM.
>>      oneOf:
>>        - items:
>>            - description: common DSS register area
>>            - description: VIDL1 light video plane
>>            - description: VID video plane
>>            - description: OVR1 overlay manager for vp1
>>            - description: OVR2 overlay manager for vp2
>>            - description: VP1 video port 1
>>            - description: VP2 video port 2
>>            - description: common1 DSS register area
>>        - items:
>>            - description: common DSS register area
>>            - description: VIDL1 light video plane
>>            - description: OVR1 overlay manager for vp1
>>            - description: VP1 video port 1
>>            - description: common1 DSS register area
>>
>> .....(Similarly for reg-names, clocks, clock-names,...)
>>
>> allOf:
>>    - if:
>>        properties:
>>          compatible:
>>            contains:
>>              const: ti,am62l-dss
>>      then:
>>        properties:
>>          clock-names:
>>            maxItems: 2
>>          clocks:
>>            maxItems: 2
>>          reg:
>>            maxItems: 5
>>      else:
>>        properties:
>>          clock-names:
>>            minItems: 3
>>          clocks:
>>            minItems: 3
>>          reg:
>>            minItems: 8
>>
>> ```
>>
>> Could you please confirm on this?

If there is no common part of each list, then this looks correct. Other
way would be the example I wrote ~2 hours ago on DT IRC (different
patchset) - so the qcom,ufs way. It depends how readable is the final
schema.

> 
> Hi Krzysztof,
> 
> Gentle ping, could you please confirm on the above design?

If you do not hear from me or other reviewer for some time after asking
"shall I do like that", just send next version implementing what you
think should be done and mentioning in changelog, that this is how you
address reviewers feedback.

Best regards,
Krzysztof

Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[Swamil Jain]

On 3/16/26 22:14, Krzysztof Kozlowski wrote:
> On 16/03/2026 13:36, Swamil Jain wrote:
>>>       description:
>>>         Addresses to each DSS memory region described in the SoC's TRM.
>>>       oneOf:
>>>         - items:
>>>             - description: common DSS register area
>>>             - description: VIDL1 light video plane
>>>             - description: VID video plane
>>>             - description: OVR1 overlay manager for vp1
>>>             - description: OVR2 overlay manager for vp2
>>>             - description: VP1 video port 1
>>>             - description: VP2 video port 2
>>>             - description: common1 DSS register area
>>>         - items:
>>>             - description: common DSS register area
>>>             - description: VIDL1 light video plane
>>>             - description: OVR1 overlay manager for vp1
>>>             - description: VP1 video port 1
>>>             - description: common1 DSS register area
>>>
>>> .....(Similarly for reg-names, clocks, clock-names,...)
>>>
>>> allOf:
>>>     - if:
>>>         properties:
>>>           compatible:
>>>             contains:
>>>               const: ti,am62l-dss
>>>       then:
>>>         properties:
>>>           clock-names:
>>>             maxItems: 2
>>>           clocks:
>>>             maxItems: 2
>>>           reg:
>>>             maxItems: 5
>>>       else:
>>>         properties:
>>>           clock-names:
>>>             minItems: 3
>>>           clocks:
>>>             minItems: 3
>>>           reg:
>>>             minItems: 8
>>>
>>> ```
>>>
>>> Could you please confirm on this?
> 
> If there is no common part of each list, then this looks correct. Other
> way would be the example I wrote ~2 hours ago on DT IRC (different
> patchset) - so the qcom,ufs way. It depends how readable is the final
> schema.
> 
>>
>> Hi Krzysztof,
>>
>> Gentle ping, could you please confirm on the above design?
> 
> If you do not hear from me or other reviewer for some time after asking
> "shall I do like that", just send next version implementing what you
> think should be done and mentioning in changelog, that this is how you
> address reviewers feedback.
> 

Thanks Krzysztof, sent a v3: 
https://lore.kernel.org/all/20260410105955.843868-1-s-jain1@ti.com/

Regards,
Swamil.

> Best regards,
> Krzysztof