Re: [PATCH V5 12/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195

[Rex-BC Chen <rex-bc.chen@mediatek.com>]

On Mon, 2022-05-02 at 16:54 +0800, AngeloGioacchino Del Regno wrote:
> Il 29/04/22 23:13, Krzysztof Kozlowski ha scritto:
> > On 28/04/2022 13:56, Rex-BC Chen wrote:
> > > To support reset of infra_ao, add the bit definitions for MT8195.
> > > The infra_ao reset includes 5 banks and 32 bits for each bank.
> > > 
> > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > ---
> > >   include/dt-bindings/reset/mt8195-resets.h | 170
> > > ++++++++++++++++++++++
> > >   1 file changed, 170 insertions(+)
> > > 
> > > diff --git a/include/dt-bindings/reset/mt8195-resets.h
> > > b/include/dt-bindings/reset/mt8195-resets.h
> > > index a26bccc8b957..463114014483 100644
> > > --- a/include/dt-bindings/reset/mt8195-resets.h
> > > +++ b/include/dt-bindings/reset/mt8195-resets.h
> > > @@ -7,6 +7,7 @@
> > >   #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
> > >   #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
> > >   
> > > +/* TOPRGU resets */
> > >   #define MT8195_TOPRGU_CONN_MCU_SW_RST          0
> > >   #define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
> > >   #define MT8195_TOPRGU_APU_SW_RST               2
> > > @@ -26,4 +27,173 @@
> > >   
> > >   #define MT8195_TOPRGU_SW_RST_NUM               16
> > >   
> > > +/* INFRA RST0 */
> > > +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST	0
> > > +#define MT8195_INFRA_RST0_RSV0			1
> > > +#define MT8195_INFRA_RST0_DISP_PWM1_SWRST	2
> > > +#define MT8195_INFRA_RST0_RSV1			3
> > > +#define MT8195_INFRA_RST0_MSDC3_SWRST		4
> > > +#define MT8195_INFRA_RST0_MSDC2_SWRST		5
> > > +#define MT8195_INFRA_RST0_MSDC1_SWRST		6
> > > +#define MT8195_INFRA_RST0_MSDC0_SWRST		7
> > > +#define MT8195_INFRA_RST0_RSV2			8
> > > +#define MT8195_INFRA_RST0_AP_DMA_SWRST		9
> > > +#define MT8195_INFRA_RST0_MIPI_D_SWRST		10
> > > +#define MT8195_INFRA_RST0_RSV3			11
> > > +#define MT8195_INFRA_RST0_RSV4			12
> > > +#define MT8195_INFRA_RST0_SSUSB_TOP_SWRST	13
> > > +#define MT8195_INFRA_RST0_DISP_PWM_SWRST	14
> > > +#define MT8195_INFRA_RST0_AUXADC_SWRST		15
> > > +#define MT8195_INFRA_RST0_RSV5			16
> > > +#define MT8195_INFRA_RST0_RSV6			17
> > > +#define MT8195_INFRA_RST0_RSV7			18
> > > +#define MT8195_INFRA_RST0_RSV8			19
> > > +#define MT8195_INFRA_RST0_RSV9			20
> > > +#define MT8195_INFRA_RST0_RSV10			21
> > > +#define MT8195_INFRA_RST0_RSV11			22
> > > +#define MT8195_INFRA_RST0_RSV12			23
> > > +#define MT8195_INFRA_RST0_RSV13			24
> > > +#define MT8195_INFRA_RST0_RSV14			25
> > > +#define MT8195_INFRA_RST0_RSV15			26
> > > +#define MT8195_INFRA_RST0_RSV16			27
> > > +#define MT8195_INFRA_RST0_RSV17			28
> > > +#define MT8195_INFRA_RST0_RSV18			29
> > > +#define MT8195_INFRA_RST0_RSV19			30
> > > +#define MT8195_INFRA_RST0_RSV20			31
> > 
> > These are not proper IDs... don't work-around usage of bits with
> > fake
> > reserved IDs...
> 
> Hello Krzysztof,
> 
> Actually, I get that it may seem that Rex is trying to cheat with
> fake
> reserved numbers... but it's really how the registers are laid out:
> there
> really are reserved bits in between used reset bits.
> 
> I don't think that the reserved bits are doing anything though, so
> the
> best way to proceed is to just remove them and map the dt-bindings
> IDs to
> the HW register's bits in the driver instead.
> Even though the current approach is very simplistic, I agree that
> this is
> not how it's supposed to be done (and I'm sort-of sad about that).
> 
> Rex, please map these values in the reset driver so that, in this
> header,
> you'll get something like:
> 
> #define MT8195_INFRA_RST0_THERM_CTRL_SWRST	0
> #define MT8195_INFRA_RST0_DISP_PWM1_SWRST	1
> #define MT8195_INFRA_RST0_MSDC3_SWRST		2
> #define .... (etc)
> 
> Cheers,
> Angelo
> 
> > 
> > Best regards,
> > Krzysztof
> 
> 

Hello Krzysztof and Angelo,

Thanks for your advice and review.
I will modify my driver using index and I will just add some reset we
curreently use.

reset.h will list like this:

#define MT8195_INFRA_RST0_THERM_CTRL_SWRST	0
#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST	1
#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST	2

For this, I will add a new mode for input argument because we alos need
to be compatible with previous reset drivers.
For input argument with different mode: 
enum MTK_RST_CTRL_MODE {
	MTK_RST_CTRL_BIT_MODE = 0,
	MTK_RST_CTRL_INDEX_MODE,
};

If register MTK_RST_CTRL_INDEX_MODE for reset controller, I will
implent new xlate function to transfer the index to offsets.

BRs,
Rex