From: Robin Murphy <robin.murphy@arm.com>
To: will@kernel.org
Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, suzuki.poulose@arm.com,
ilkka@os.amperecomputing.com, bwicaksono@nvidia.com,
YWan@nvidia.com, rwiley@nvidia.com,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Subject: [PATCH 4/5] dt-bindings/perf: Add Arm CoreSight PMU
Date: Tue, 5 Dec 2023 16:51:57 +0000 [thread overview]
Message-ID: <bbb4262065cfc906f98165cac074e86dce19599e.1701793996.git.robin.murphy@arm.com> (raw)
In-Reply-To: <cover.1701793996.git.robin.murphy@arm.com>
Add a binding for implementations of the Arm CoreSight Performance
Monitoring Unit Architecture. Not to be confused with CoreSight debug
and trace, the PMU architecture defines a standard MMIO interface for
event counters similar to the CPU PMU architecture, where the
implementation and most of its features are discoverable through ID
registers.
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Conor Dooley <conor+dt@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
.../bindings/perf/arm,coresight-pmu.yaml | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml
diff --git a/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml
new file mode 100644
index 000000000000..12c7b28eee35
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Coresight Performance Monitoring Unit Architecture
+
+maintainers:
+ - Robin Murphy <robin.murphy@arm.com>
+
+properties:
+ compatible:
+ const: arm,coresight-pmu
+
+ reg:
+ items:
+ - description: Register page 0
+ - description: Register page 1 (if dual-page extension implemented)
+ minItems: 1
+
+ interrupts:
+ items:
+ - description: Overflow interrupt
+
+ cpus:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ description: List of CPUs with which the PMU is associated, if applicable
+
+ arm,64-bit-atomic:
+ type: boolean
+ description: Register accesses are single-copy atomic at doubleword granularity
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
--
2.39.2.101.g768bb238c484.dirty
next prev parent reply other threads:[~2023-12-05 16:52 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 16:51 [PATCH 0/5] perf/arm_cspmu: Add devicetree support Robin Murphy
2023-12-05 16:51 ` [PATCH 1/5] perf/arm_cspmu: Simplify initialisation Robin Murphy
2023-12-07 2:16 ` Ilkka Koskinen
2023-12-05 16:51 ` [PATCH 2/5] perf/arm_cspmu: Simplify attribute groups Robin Murphy
2023-12-07 2:47 ` Ilkka Koskinen
2023-12-05 16:51 ` [PATCH 3/5] perf/arm_cspmu: Simplify counter reset Robin Murphy
2023-12-07 2:15 ` Ilkka Koskinen
2023-12-05 16:51 ` Robin Murphy [this message]
2023-12-08 19:33 ` [PATCH 4/5] dt-bindings/perf: Add Arm CoreSight PMU Rob Herring
2023-12-08 21:56 ` Robin Murphy
2023-12-05 16:51 ` [PATCH 5/5] perf/arm_cspmu: Add devicetree support Robin Murphy
2023-12-06 23:43 ` Ilkka Koskinen
2023-12-07 9:43 ` Robin Murphy
2023-12-08 6:35 ` Ilkka Koskinen
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