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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab7d45572efsm52481166b.5.2025.02.10.07.23.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 07:24:00 -0800 (PST) Message-ID: Date: Mon, 10 Feb 2025 16:23:58 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs To: neil.armstrong@linaro.org, Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250207-topic-sm8650-pmu-ppi-partition-v1-0-dd3ba17b3eea@linaro.org> <20250207-topic-sm8650-pmu-ppi-partition-v1-2-dd3ba17b3eea@linaro.org> <6aa71142-3b1d-476f-9c78-1207fbbed3f5@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <6aa71142-3b1d-476f-9c78-1207fbbed3f5@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: aT1kUOkVF7k0Uuanh0eretENSafcxGQf X-Proofpoint-GUID: aT1kUOkVF7k0Uuanh0eretENSafcxGQf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_08,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 spamscore=0 mlxlogscore=737 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100127 On 9.02.2025 3:44 PM, Neil Armstrong wrote: > On 07/02/2025 21:30, Konrad Dybcio wrote: >> On 7.02.2025 11:31 AM, Neil Armstrong wrote: >>> The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper >>> interrupt partition maps and use the 4th interrupt cell to pass the >>> partition phandle for each ARM PMU node. >>> >>> Signed-off-by: Neil Armstrong >>> --- >> >>> @@ -5309,6 +5309,20 @@ intc: interrupt-controller@17100000 { >>>               #size-cells = <2>; >>>               ranges; >>>   +            ppi-partitions { >>> +                ppi_cluster0: interrupt-partition-0 { >>> +                    affinity = <&cpu0 &cpu1>; >>> +                }; >>> + >>> +                ppi_cluster1: interrupt-partition-1 { >>> +                    affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; >>> +                }; >>> + >>> +                ppi_cluster2: interrupt-partition-2 { >>> +                    affinity = <&cpu7>; >>> +                }; >> >> I'm not sure this is accurate. >> >> I *think* it's cores 0-1 and 2-7, but I can't find a concrete answer > > Core 7 is a Cortex-X4, and has a dedicated PMU node, look at the cpu compatibles. Look at what these compatibles do in code. Nothing special for the X. Konrad