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Wed, 16 Oct 2024 05:13:41 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49G5DRlZ025633 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 16 Oct 2024 05:13:27 GMT Received: from [10.216.49.154] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Oct 2024 22:13:23 -0700 Message-ID: Date: Wed, 16 Oct 2024 10:43:19 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes Content-Language: en-US To: Dmitry Baryshkov , Manivannan Sadhasivam CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , , , , , , , References: <20240209075716.GA12035@thinkpad> <20241001101622.ys36slymgjbaz26q@thinkpad> <8459161B-87B8-481F-AE71-3D5156B1CA56@linaro.org> <20241001141948.g74rn6777ywvtcmx@thinkpad> <9c24ba5d-431a-c45e-ce1c-3541eac7d017@quicinc.com> <20241012124334.4gsspgtuud4uudop@thinkpad> <7yzjgqitjvfwricftcpelktwjbgwkjuibwkpodjd6x4gwkjkw3@wkeqp6lqwfqv> From: Krishna Chaitanya Chundru In-Reply-To: <7yzjgqitjvfwricftcpelktwjbgwkjuibwkpodjd6x4gwkjkw3@wkeqp6lqwfqv> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UYdiqJwZ8aOVuaWU5tqd-kEb_xeY5UkS X-Proofpoint-GUID: UYdiqJwZ8aOVuaWU5tqd-kEb_xeY5UkS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410160032 On 10/14/2024 4:55 AM, Dmitry Baryshkov wrote: > On Sat, Oct 12, 2024 at 06:13:34PM +0530, Manivannan Sadhasivam wrote: >> On Fri, Oct 11, 2024 at 05:24:29PM +0530, Krishna Chaitanya Chundru wrote: >> >> [...] >> >>>>> The logic here is that the fixed endpoints in the switch will get an unique SID >>>>> and the devices getting attached to slots will share the same SID of the bus >>>>> (this is the usual case with all Qcom SoCs). >>>>> >>>>> But I guess we would need 'iommu-map-mask' as well. Hope this addresses your >>>>> concern. >>>> >>>> Yes, thank you! >>>> >>> Hi dimitry & mani, >>> >>> This particular board variant doesn't expose any open slots to connect >>> a different endpoints like another switch(which might have BDF unknown >>> to us) so static table should be fine for this board variant. >>> >>> I tries to add iommu-map-mask property, the issue with that property is >>> that the driver is applying the mask to the bdf before searching for the >>> entry in the table. If I use a mask value which satisfies all the >>> entries in the table ( mask as 0x718) and if a new bdf is enumerated >>> lets say 0x600 due to mask 0x718 its value is again 0x600 only. >>> >>> Can we skip iommu-map-mask property and use only static table for this >>> board as we know this board doesn't expose any open slots. >>> >> >> Hmm, I was not aware that it doesn't have open slots. Fine with me then. > > It doesn't feature open slots, but it has two PCIe connections on HS2 / > HS3. Users might attach external PCIe devices. > > Krishna, could you please clarify, how those two connections are routed? > For this qps615 board to one of the downstream port (pcie to usb) usb hub is connected and to the other downstream port NVMe will be connected. - Krishna Chaitanya.