From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DDB73DEAFA; Mon, 18 May 2026 07:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779087639; cv=none; b=nkoemHXAAnfJKUN5zZeawNs9ySymhDB5xlxqP10UO8IXMqJjTjgG1I5NdBq63884/4l5oVq34yJPW8qZ7YTN2BVS7t7aT05vGhNomaaDr16bMilRR+/fBchYtS5VDhci500EjgCSNsJ5N8MrpAkw2//2WOxsA9oqhE3LzH3xKqQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779087639; c=relaxed/simple; bh=lelqDmyTg+5CXbISPM5moYnepKJes/RZlk8bJJ8cNDY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=tCXkpH0Q5aGq67Kc27EW8VQB4GmhkaLDpwwComwNKZCxNVVA3iK67mQ7rde0zshjzav9uItg9QqsCS/hiqbtF5OqbDXVGIZ4hz3M5oU3CIHjyQOCqY3k3K1SAx41Biy0gcyqDaVlIDLQnSbK3BPgMwlVrNraC+A8lh66uolRuBI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h5q9MbOj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h5q9MbOj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 720B6C2BCB7; Mon, 18 May 2026 07:00:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779087638; bh=lelqDmyTg+5CXbISPM5moYnepKJes/RZlk8bJJ8cNDY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=h5q9MbOjdh4olgCXG1BFaG463QsXkHevGJRiyCAGpJKX7mqipj8BWMBMM1IV8Yfyf nhmkE62DjE+xKrnlsFeMlceD//GQGzRZBHtvhtBjRp3plw7L3gMvNoDJ0ZxlHtLETx BvtSZ5l4hVmWv9IWCeN2bCj3tj/J5C7lZ0AL2yK7LKydDp1h7NyJ68UYa7yPDt2BU3 MYoXZWhyKp3w9B3A0NxJl+TSVeq5jGZUqrOzwe5uDvn9hA4n49Q/T3Uk2sM264ORIp /PlVLhB1GJgPCbbFTSBaT86PUir+GqRNu8htNOIZgR9pINeZ2bYJKWSqXgvdqeuZbe jzweZfy1j55xA== Message-ID: Date: Mon, 18 May 2026 09:00:33 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] dt-bindings: clock: qcom: Add QREF regulator supplies for glymur To: Qiang Yu Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com References: <20260506-qref_vote_0506-v3-0-5ab71d2e6f16@oss.qualcomm.com> <20260506-qref_vote_0506-v3-1-5ab71d2e6f16@oss.qualcomm.com> <20260514-outgoing-literate-dove-2e2a73@quoll> <408f587b-76c2-4fdd-bbe1-89414270b4ee@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; keydata= xsFNBFVDQq4BEAC6KeLOfFsAvFMBsrCrJ2bCalhPv5+KQF2PS2+iwZI8BpRZoV+Bd5kWvN79 cFgcqTTuNHjAvxtUG8pQgGTHAObYs6xeYJtjUH0ZX6ndJ33FJYf5V3yXqqjcZ30FgHzJCFUu JMp7PSyMPzpUXfU12yfcRYVEMQrmplNZssmYhiTeVicuOOypWugZKVLGNm0IweVCaZ/DJDIH gNbpvVwjcKYrx85m9cBVEBUGaQP6AT7qlVCkrf50v8bofSIyVa2xmubbAwwFA1oxoOusjPIE J3iadrwpFvsZjF5uHAKS+7wHLoW9hVzOnLbX6ajk5Hf8Pb1m+VH/E8bPBNNYKkfTtypTDUCj NYcd27tjnXfG+SDs/EXNUAIRefCyvaRG7oRYF3Ec+2RgQDRnmmjCjoQNbFrJvJkFHlPeHaeS BosGY+XWKydnmsfY7SSnjAzLUGAFhLd/XDVpb1Een2XucPpKvt9ORF+48gy12FA5GduRLhQU vK4tU7ojoem/G23PcowM1CwPurC8sAVsQb9KmwTGh7rVz3ks3w/zfGBy3+WmLg++C2Wct6nM Pd8/6CBVjEWqD06/RjI2AnjIq5fSEH/BIfXXfC68nMp9BZoy3So4ZsbOlBmtAPvMYX6U8VwD TNeBxJu5Ex0Izf1NV9CzC3nNaFUYOY8KfN01X5SExAoVTr09ewARAQABzSVLcnp5c3p0b2Yg S296bG93c2tpIDxrcnprQGtlcm5lbC5vcmc+wsGVBBMBCgA/AhsDBgsJCAcDAgYVCAIJCgsE FgIDAQIeAQIXgBYhBJvQfg4MUfjVlne3VBuTQ307QWKbBQJoF1BKBQkWlnSaAAoJEBuTQ307 QWKbHukP/3t4tRp/bvDnxJfmNdNVn0gv9ep3L39IntPalBFwRKytqeQkzAju0whYWg+R/rwp +r2I1Fzwt7+PTjsnMFlh1AZxGDmP5MFkzVsMnfX1lGiXhYSOMP97XL6R1QSXxaWOpGNCDaUl ajorB0lJDcC0q3xAdwzRConxYVhlgmTrRiD8oLlSCD5baEAt5Zw17UTNDnDGmZQKR0fqLpWy 786Lm5OScb7DjEgcA2PRm17st4UQ1kF0rQHokVaotxRM74PPDB8bCsunlghJl1DRK9s1aSuN hL1Pv9VD8b4dFNvCo7b4hfAANPU67W40AaaGZ3UAfmw+1MYyo4QuAZGKzaP2ukbdCD/DYnqi tJy88XqWtyb4UQWKNoQqGKzlYXdKsldYqrLHGoMvj1UN9XcRtXHST/IaLn72o7j7/h/Ac5EL 8lSUVIG4TYn59NyxxAXa07Wi6zjVL1U11fTnFmE29ALYQEXKBI3KUO1A3p4sQWzU7uRmbuxn naUmm8RbpMcOfa9JjlXCLmQ5IP7Rr5tYZUCkZz08LIfF8UMXwH7OOEX87Y++EkAB+pzKZNNd hwoXulTAgjSy+OiaLtuCys9VdXLZ3Zy314azaCU3BoWgaMV0eAW/+gprWMXQM1lrlzvwlD/k whyy9wGf0AEPpLssLVt9VVxNjo6BIkt6d1pMg6mHsUEVzsFNBFVDXDQBEADNkrQYSREUL4D3 Gws46JEoZ9HEQOKtkrwjrzlw/tCmqVzERRPvz2Xg8n7+HRCrgqnodIYoUh5WsU84N03KlLue MNsWLJBvBaubYN4JuJIdRr4dS4oyF1/fQAQPHh8Thpiz0SAZFx6iWKB7Qrz3OrGCjTPcW6ei OMheesVS5hxietSmlin+SilmIAPZHx7n242u6kdHOh+/SyLImKn/dh9RzatVpUKbv34eP1wA GldWsRxbf3WP9pFNObSzI/Bo3kA89Xx2rO2roC+Gq4LeHvo7ptzcLcrqaHUAcZ3CgFG88CnA 6z6lBZn0WyewEcPOPdcUB2Q7D/NiUY+HDiV99rAYPJztjeTrBSTnHeSBPb+qn5ZZGQwIdUW9 YegxWKvXXHTwB5eMzo/RB6vffwqcnHDoe0q7VgzRRZJwpi6aMIXLfeWZ5Wrwaw2zldFuO4Dt 91pFzBSOIpeMtfgb/Pfe/a1WJ/GgaIRIBE+NUqckM+3zJHGmVPqJP/h2Iwv6nw8U+7Yyl6gU BLHFTg2hYnLFJI4Xjg+AX1hHFVKmvl3VBHIsBv0oDcsQWXqY+NaFahT0lRPjYtrTa1v3tem/ JoFzZ4B0p27K+qQCF2R96hVvuEyjzBmdq2esyE6zIqftdo4MOJho8uctOiWbwNNq2U9pPWmu 4vXVFBYIGmpyNPYzRm0QPwARAQABwsF8BBgBCgAmAhsMFiEEm9B+DgxR+NWWd7dUG5NDfTtB YpsFAmgXUF8FCRaWWyoACgkQG5NDfTtBYptO0w//dlXJs5/42hAXKsk+PDg3wyEFb4NpyA1v qmx7SfAzk9Hf6lWwU1O6AbqNMbh6PjEwadKUk1m04S7EjdQLsj/MBSgoQtCT3MDmWUUtHZd5 RYIPnPq3WVB47GtuO6/u375tsxhtf7vt95QSYJwCB+ZUgo4T+FV4hquZ4AsRkbgavtIzQisg Dgv76tnEv3YHV8Jn9mi/Bu0FURF+5kpdMfgo1sq6RXNQ//TVf8yFgRtTUdXxW/qHjlYURrm2 H4kutobVEIxiyu6m05q3e9eZB/TaMMNVORx+1kM3j7f0rwtEYUFzY1ygQfpcMDPl7pRYoJjB dSsm0ZuzDaCwaxg2t8hqQJBzJCezTOIkjHUsWAK+tEbU4Z4SnNpCyM3fBqsgYdJxjyC/tWVT AQ18NRLtPw7tK1rdcwCl0GFQHwSwk5pDpz1NH40e6lU+NcXSeiqkDDRkHlftKPV/dV+lQXiu jWt87ecuHlpL3uuQ0ZZNWqHgZoQLXoqC2ZV5KrtKWb/jyiFX/sxSrodALf0zf+tfHv0FZWT2 zHjUqd0t4njD/UOsuIMOQn4Ig0SdivYPfZukb5cdasKJukG1NOpbW7yRNivaCnfZz6dTawXw XRIV/KDsHQiyVxKvN73bThKhONkcX2LWuD928tAR6XMM2G5ovxLe09vuOzzfTWQDsm++9UKF a/A= In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 18/05/2026 05:50, Qiang Yu wrote: > On Sun, May 17, 2026 at 10:27:39AM +0200, Krzysztof Kozlowski wrote: >> On 17/05/2026 07:39, Qiang Yu wrote: >>> On Thu, May 14, 2026 at 12:22:17PM +0200, Krzysztof Kozlowski wrote: >>>> On Wed, May 06, 2026 at 01:43:51AM -0700, Qiang Yu wrote: >>>>> Add regulator supply properties for the Glymur TCSR QREF/REFGEN blocks >>>>> required by clkref clocks. >>>>> >>>>> The vdda-qreftx*, vdda-qrefrpt*, and vdda-qrefrx* supplies map to common >>>>> QREF TX/RPT/RX components, while SoC-specific topology and instance count >>>>> differ. Document them here for qcom,glymur-tcsr. >>>>> >>>>> Signed-off-by: Qiang Yu >>>>> --- >>>>> .../bindings/clock/qcom,sm8550-tcsr.yaml | 57 ++++++++++++++++++++++ >>>>> 1 file changed, 57 insertions(+) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>>>> index 1ccdf4b0f5dd..57921cb63230 100644 >>>>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>>>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>>>> @@ -51,6 +51,63 @@ properties: >>>>> '#reset-cells': >>>>> const: 1 >>>>> >>>>> + vdda-refgen-0p9-supply: true >>>>> + vdda-refgen-1p2-supply: true >>>>> + vdda-qrefrx0-0p9-supply: true >>>>> + vdda-qrefrx1-0p9-supply: true >>>>> + vdda-qrefrx2-0p9-supply: true >>>>> + vdda-qrefrx4-0p9-supply: true >>>>> + vdda-qrefrx5-0p9-supply: true >>>>> + vdda-qreftx0-0p9-supply: true >>>>> + vdda-qreftx0-1p2-supply: true >>>>> + vdda-qreftx1-0p9-supply: true >>>>> + vdda-qrefrpt0-0p9-supply: true >>>>> + vdda-qrefrpt1-0p9-supply: true >>>>> + vdda-qrefrpt2-0p9-supply: true >>>>> + vdda-qrefrpt3-0p9-supply: true >>>>> + vdda-qrefrpt4-0p9-supply: true >>>> >>>> Either I do not understand your previous explanation: >>>> CXO -> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 -> PCIe4_PHY >>>> >>>> or this is still wrong. There is no TCSR here, so this proves nothing. >>>> If TCSR is TX0, then you do not have five of them... >>>> >>>> My previous comment stay - you are not describing the actual hardware >>>> here. >>>> >>> The CXO network "-> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 ->" is referred to >>> as the QREF block, and each component is controlled by the tcsr_clkref_en >>> registers. >> >> Still no clue what this -> relation is. Again, describe the hardware. >> >>> >>> If a PHY receives its reference clock from QREF, it will have a clkref_en >>> register. However, this register may be located in different regions >>> depending on the target. On glymur it resides in TCSR, so I added these >>> LDOs QREF required in tcsr yaml. >> Registers are not described as supplies. > > I'm not descirbing register as supply. > > tx0-0p9/1p2 rpt0-0p9 rpt1-0p9 rpt2-0p9 rx2-0p9 > | | | | | > | | | | | > CXO -> TX0 -------> RPT0 ------> RPT1 -> RPT2 -----> RX2 -> PCIe4_PHY > | | | | | > | | | | | > ---------------------------------------------------tcsr_clkref_en > > These components(TX/RTP/RX) can be disabled/enabled by tcsr_clkref_en > register, and they require power supplies. So I told you more than once - none of these are supplies to the TCSR. You clearly misunderstand what a supply is. Best regards, Krzysztof