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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Dinh Nguyen <dinguyen@kernel.org>, jh80.chung@samsung.com
Cc: ulf.hansson@linaro.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
	sboyd@kernel.org, linux-mmc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCHv5 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
Date: Thu, 20 Oct 2022 14:20:07 -0400	[thread overview]
Message-ID: <bc0a9297-7adb-7cdb-e5ee-1d6e80eddb04@linaro.org> (raw)
In-Reply-To: <20221019170657.68014-2-dinguyen@kernel.org>

On 19/10/2022 13:06, Dinh Nguyen wrote:

Thank you for your patch. There is something to discuss/improve.

> -allOf:
> -  - $ref: "synopsys-dw-mshc-common.yaml#"
> -
>  maintainers:
>    - Ulf Hansson <ulf.hansson@linaro.org>
>  
> @@ -38,6 +35,35 @@ properties:
>        - const: biu
>        - const: ciu
>  
> +  altr,sysmgr-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to the sysmgr node
> +          - description: register offset that controls the SDMMC clock phase
> +          - description: register shift for the smplsel(drive in) setting
> +    description:
> +      Contains the phandle to System Manager block that contains
> +      the SDMMC clock-phase control register. The first value is the pointer
> +      to the sysmgr, the 2nd value is the register offset for the SDMMC
> +      clock phase register, and the 3rd value is the bit shift for the
> +      smplsel(drive in) setting.
> +
> +allOf:
> +  - $ref: "synopsys-dw-mshc-common.yaml#"

If there is going to be resend, please drop quotes here.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


  parent reply	other threads:[~2022-10-20 18:20 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-19 17:06 [PATCHv5 0/6] arm: socfpga: use clk-phase-sd-hs Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen
2022-10-19 23:31   ` Rob Herring
2022-10-20 23:01     ` Rob Herring
2022-10-20 18:20   ` Krzysztof Kozlowski [this message]
2022-10-19 17:06 ` [PATCHv5 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 3/6] arm: " Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen
2022-10-21 13:32   ` Krzysztof Kozlowski
2022-10-21 15:17     ` Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Dinh Nguyen

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