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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id s9-20020ac24649000000b004cb08757441sm3278680lfo.199.2023.01.12.06.42.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 06:42:23 -0800 (PST) Message-ID: Date: Thu, 12 Jan 2023 15:42:21 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 12/13] clk: qcom: cpu-8996: change setup sequence to follow vendor kernel Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20230111192004.2509750-1-dmitry.baryshkov@linaro.org> <20230111192004.2509750-13-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20230111192004.2509750-13-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11.01.2023 20:20, Dmitry Baryshkov wrote: > Add missing register writes to CPU clocks setup procedure. This makes it > follow the setup procedure used in msm-3.18 kernel. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > drivers/clk/qcom/clk-cpu-8996.c | 31 +++++++++++++++++++++++++++++-- > 1 file changed, 29 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c > index b53cddc4bca3..78a18b95c48b 100644 > --- a/drivers/clk/qcom/clk-cpu-8996.c > +++ b/drivers/clk/qcom/clk-cpu-8996.c > @@ -76,10 +76,16 @@ enum _pmux_input { > #define PWRCL_REG_OFFSET 0x0 > #define PERFCL_REG_OFFSET 0x80000 > #define MUX_OFFSET 0x40 > +#define CLK_CTL_OFFSET 0x44 > +#define CLK_CTL_AUTO_CLK_SEL BIT(8) > #define ALT_PLL_OFFSET 0x100 > #define SSSCTL_OFFSET 0x160 > +#define PSCTL_OFFSET 0x164 > > #define PMUX_MASK 0x3 > +#define MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4) > +#define MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \ > + FIELD_PREP(MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03) > > static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { > [PLL_OFF_L_VAL] = 0x04, > @@ -439,6 +445,14 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, > /* Ensure write goes through before PLLs are reconfigured */ > udelay(5); > > + /* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */ > + regmap_update_bits(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, > + MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, > + MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL); > + regmap_update_bits(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, > + MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, > + MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL); > + > clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); > clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); > clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); > @@ -447,11 +461,24 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, > /* Wait for PLL(s) to lock */ > udelay(50); > > + /* Enable auto clock selection for both clusters */ > + regmap_update_bits(regmap, PWRCL_REG_OFFSET + CLK_CTL_OFFSET, > + CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL); > + regmap_update_bits(regmap, PERFCL_REG_OFFSET + CLK_CTL_OFFSET, > + CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL); > + > + /* Ensure write goes through before muxes are switched */ > + udelay(5); > + > qcom_cpu_clk_msm8996_acd_init(regmap); > > + /* Pulse swallower and soft-start settings */ > + regmap_write(regmap, PWRCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005); > + regmap_write(regmap, PERFCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005); > + > /* Switch clusters to use the ACD leg */ > - regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2); > - regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2); > + regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x32); > + regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x32); > > for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { > ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]);