* [PATCH 0/4] soc: qcom: llcc: Add support for Glymur SoC
@ 2025-11-21 9:53 Pankaj Patil
2025-11-21 9:53 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block Pankaj Patil
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Pankaj Patil @ 2025-11-21 9:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Conor Dooley, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
sibi.sankar, rajendra.nayak
Glymur SoC uses the Last Level Cache Controller (LLCC) as its
system cache controller, update the device-tree bindings and
SCT configuration data in the LLCC driver.
Enabled additional use case IDs defined in
include/linux/soc/qcom/llcc-qcom.h:
OOBM_NS
OOBM_S
VIDSC_VSP1
PCIE_TCU
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
Pankaj Patil (4):
dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
soc: qcom: llcc: Enable additional usecase id for Glymur
soc: qcom: llcc: Fix usecase id macro alignment
soc: qcom: llcc-qcom: Add support for Glymur
.../devicetree/bindings/cache/qcom,llcc.yaml | 43 +++++
drivers/soc/qcom/llcc-qcom.c | 207 +++++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 152 +++++++--------
3 files changed, 328 insertions(+), 74 deletions(-)
---
base-commit: b179ce312bafcb8c68dc718e015aee79b7939ff0
change-id: 20251029-glymur_llcc_enablement-6a812c08f4c1
Best regards,
--
Pankaj Patil <pankaj.patil@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/4] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
2025-11-21 9:53 [PATCH 0/4] soc: qcom: llcc: Add support for Glymur SoC Pankaj Patil
@ 2025-11-21 9:53 ` Pankaj Patil
2025-11-21 10:35 ` Krzysztof Kozlowski
2025-11-21 9:53 ` [PATCH 2/4] soc: qcom: llcc: Enable additional usecase id for Glymur Pankaj Patil
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Pankaj Patil @ 2025-11-21 9:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Conor Dooley, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
sibi.sankar, rajendra.nayak
Document the Last Level Cache Controller on Glymur SoC
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
.../devicetree/bindings/cache/qcom,llcc.yaml | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index a620a2ff5c56..74a81baae0e7 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,glymur-llcc
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
@@ -84,6 +85,48 @@ allOf:
items:
- const: llcc0_base
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,glymur-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC2 base register region
+ - description: LLCC3 base register region
+ - description: LLCC4 base register region
+ - description: LLCC5 base register region
+ - description: LLCC6 base register region
+ - description: LLCC7 base register region
+ - description: LLCC8 base register region
+ - description: LLCC9 base register region
+ - description: LLCC10 base register region
+ - description: LLCC11 base register region
+ - description: LLCC broadcast base register region
+ - description: LLCC broadcast AND register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc2_base
+ - const: llcc3_base
+ - const: llcc4_base
+ - const: llcc5_base
+ - const: llcc6_base
+ - const: llcc7_base
+ - const: llcc7_base
+ - const: llcc8_base
+ - const: llcc9_base
+ - const: llcc10_base
+ - const: llcc11_base
+ - const: llcc_broadcast_base
+ - const: llcc_broadcast_and_base
+
- if:
properties:
compatible:
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/4] soc: qcom: llcc: Enable additional usecase id for Glymur
2025-11-21 9:53 [PATCH 0/4] soc: qcom: llcc: Add support for Glymur SoC Pankaj Patil
2025-11-21 9:53 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block Pankaj Patil
@ 2025-11-21 9:53 ` Pankaj Patil
2025-11-21 10:37 ` Krzysztof Kozlowski
2025-11-21 9:53 ` [PATCH 3/4] soc: qcom: llcc: Fix usecase id macro alignment Pankaj Patil
2025-11-21 9:53 ` [PATCH 4/4] soc: qcom: llcc-qcom: Add support for Glymur Pankaj Patil
3 siblings, 1 reply; 10+ messages in thread
From: Pankaj Patil @ 2025-11-21 9:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Conor Dooley, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
sibi.sankar, rajendra.nayak
Update the list of usecase id's to enable additional clients
for Glymur SoC
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
include/linux/soc/qcom/llcc-qcom.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 0287f9182c4d..8243ab3a12a8 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -74,13 +74,17 @@
#define LLCC_CAMSRTIP 73
#define LLCC_CAMRTRF 74
#define LLCC_CAMSRTRF 75
+#define LLCC_OOBM_NS 81
+#define LLCC_OOBM_S 82
#define LLCC_VIDEO_APV 83
#define LLCC_COMPUTE1 87
#define LLCC_CPUSS_OPP 88
#define LLCC_CPUSSMPAM 89
+#define LLCC_VIDSC_VSP1 91
#define LLCC_CAM_IPE_STROV 92
#define LLCC_CAM_OFE_STROV 93
#define LLCC_CPUSS_HEU 94
+#define LLCC_PCIE_TCU 97
#define LLCC_MDM_PNG_FIXED 100
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] soc: qcom: llcc: Fix usecase id macro alignment
2025-11-21 9:53 [PATCH 0/4] soc: qcom: llcc: Add support for Glymur SoC Pankaj Patil
2025-11-21 9:53 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block Pankaj Patil
2025-11-21 9:53 ` [PATCH 2/4] soc: qcom: llcc: Enable additional usecase id for Glymur Pankaj Patil
@ 2025-11-21 9:53 ` Pankaj Patil
2025-11-21 10:36 ` Krzysztof Kozlowski
2025-11-21 9:53 ` [PATCH 4/4] soc: qcom: llcc-qcom: Add support for Glymur Pankaj Patil
3 siblings, 1 reply; 10+ messages in thread
From: Pankaj Patil @ 2025-11-21 9:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Conor Dooley, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
sibi.sankar, rajendra.nayak
Fixed spacing for usecase id macro along the
column length
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
include/linux/soc/qcom/llcc-qcom.h | 156 ++++++++++++++++++-------------------
1 file changed, 78 insertions(+), 78 deletions(-)
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 8243ab3a12a8..30b436d0140a 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -8,84 +8,84 @@
#ifndef __LLCC_QCOM__
#define __LLCC_QCOM__
-#define LLCC_CPUSS 1
-#define LLCC_VIDSC0 2
-#define LLCC_VIDSC1 3
-#define LLCC_ROTATOR 4
-#define LLCC_VOICE 5
-#define LLCC_AUDIO 6
-#define LLCC_MDMHPGRW 7
-#define LLCC_MDM 8
-#define LLCC_MODHW 9
-#define LLCC_CMPT 10
-#define LLCC_GPUHTW 11
-#define LLCC_GPU 12
-#define LLCC_MMUHWT 13
-#define LLCC_CMPTDMA 15
-#define LLCC_DISP 16
-#define LLCC_VIDFW 17
-#define LLCC_CAMFW 18
-#define LLCC_MDMHPFX 20
-#define LLCC_MDMPNG 21
-#define LLCC_AUDHW 22
-#define LLCC_NPU 23
-#define LLCC_WLHW 24
-#define LLCC_PIMEM 25
-#define LLCC_ECC 26
-#define LLCC_CVP 28
-#define LLCC_MODPE 29
-#define LLCC_APTCM 30
-#define LLCC_WRCACHE 31
-#define LLCC_CVPFW 32
-#define LLCC_CPUSS1 33
-#define LLCC_CAMEXP0 34
-#define LLCC_CPUMTE 35
-#define LLCC_CPUHWT 36
-#define LLCC_MDMCLAD2 37
-#define LLCC_CAMEXP1 38
-#define LLCC_CMPTHCP 39
-#define LLCC_LCPDARE 40
-#define LLCC_AENPU 45
-#define LLCC_ISLAND1 46
-#define LLCC_ISLAND2 47
-#define LLCC_ISLAND3 48
-#define LLCC_ISLAND4 49
-#define LLCC_CAMEXP2 50
-#define LLCC_CAMEXP3 51
-#define LLCC_CAMEXP4 52
-#define LLCC_DISP_WB 53
-#define LLCC_DISP_1 54
-#define LLCC_VIEYE 57
-#define LLCC_VIDPTH 58
-#define LLCC_GPUMV 59
-#define LLCC_EVA_LEFT 60
-#define LLCC_EVA_RIGHT 61
-#define LLCC_EVAGAIN 62
-#define LLCC_VIPTH 63
-#define LLCC_VIDVSP 64
-#define LLCC_DISP_LEFT 65
-#define LLCC_DISP_RIGHT 66
-#define LLCC_EVCS_LEFT 67
-#define LLCC_EVCS_RIGHT 68
-#define LLCC_SPAD 69
-#define LLCC_VIDDEC 70
-#define LLCC_CAMOFE 71
-#define LLCC_CAMRTIP 72
-#define LLCC_CAMSRTIP 73
-#define LLCC_CAMRTRF 74
-#define LLCC_CAMSRTRF 75
-#define LLCC_OOBM_NS 81
-#define LLCC_OOBM_S 82
-#define LLCC_VIDEO_APV 83
-#define LLCC_COMPUTE1 87
-#define LLCC_CPUSS_OPP 88
-#define LLCC_CPUSSMPAM 89
-#define LLCC_VIDSC_VSP1 91
-#define LLCC_CAM_IPE_STROV 92
-#define LLCC_CAM_OFE_STROV 93
-#define LLCC_CPUSS_HEU 94
-#define LLCC_PCIE_TCU 97
-#define LLCC_MDM_PNG_FIXED 100
+#define LLCC_CPUSS 1
+#define LLCC_VIDSC0 2
+#define LLCC_VIDSC1 3
+#define LLCC_ROTATOR 4
+#define LLCC_VOICE 5
+#define LLCC_AUDIO 6
+#define LLCC_MDMHPGRW 7
+#define LLCC_MDM 8
+#define LLCC_MODHW 9
+#define LLCC_CMPT 10
+#define LLCC_GPUHTW 11
+#define LLCC_GPU 12
+#define LLCC_MMUHWT 13
+#define LLCC_CMPTDMA 15
+#define LLCC_DISP 16
+#define LLCC_VIDFW 17
+#define LLCC_CAMFW 18
+#define LLCC_MDMHPFX 20
+#define LLCC_MDMPNG 21
+#define LLCC_AUDHW 22
+#define LLCC_NPU 23
+#define LLCC_WLHW 24
+#define LLCC_PIMEM 25
+#define LLCC_ECC 26
+#define LLCC_CVP 28
+#define LLCC_MODPE 29
+#define LLCC_APTCM 30
+#define LLCC_WRCACHE 31
+#define LLCC_CVPFW 32
+#define LLCC_CPUSS1 33
+#define LLCC_CAMEXP0 34
+#define LLCC_CPUMTE 35
+#define LLCC_CPUHWT 36
+#define LLCC_MDMCLAD2 37
+#define LLCC_CAMEXP1 38
+#define LLCC_CMPTHCP 39
+#define LLCC_LCPDARE 40
+#define LLCC_AENPU 45
+#define LLCC_ISLAND1 46
+#define LLCC_ISLAND2 47
+#define LLCC_ISLAND3 48
+#define LLCC_ISLAND4 49
+#define LLCC_CAMEXP2 50
+#define LLCC_CAMEXP3 51
+#define LLCC_CAMEXP4 52
+#define LLCC_DISP_WB 53
+#define LLCC_DISP_1 54
+#define LLCC_VIEYE 57
+#define LLCC_VIDPTH 58
+#define LLCC_GPUMV 59
+#define LLCC_EVA_LEFT 60
+#define LLCC_EVA_RIGHT 61
+#define LLCC_EVAGAIN 62
+#define LLCC_VIPTH 63
+#define LLCC_VIDVSP 64
+#define LLCC_DISP_LEFT 65
+#define LLCC_DISP_RIGHT 66
+#define LLCC_EVCS_LEFT 67
+#define LLCC_EVCS_RIGHT 68
+#define LLCC_SPAD 69
+#define LLCC_VIDDEC 70
+#define LLCC_CAMOFE 71
+#define LLCC_CAMRTIP 72
+#define LLCC_CAMSRTIP 73
+#define LLCC_CAMRTRF 74
+#define LLCC_CAMSRTRF 75
+#define LLCC_OOBM_NS 81
+#define LLCC_OOBM_S 82
+#define LLCC_VIDEO_APV 83
+#define LLCC_COMPUTE1 87
+#define LLCC_CPUSS_OPP 88
+#define LLCC_CPUSSMPAM 89
+#define LLCC_VIDSC_VSP1 91
+#define LLCC_CAM_IPE_STROV 92
+#define LLCC_CAM_OFE_STROV 93
+#define LLCC_CPUSS_HEU 94
+#define LLCC_PCIE_TCU 97
+#define LLCC_MDM_PNG_FIXED 100
/**
* struct llcc_slice_desc - Cache slice descriptor
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/4] soc: qcom: llcc-qcom: Add support for Glymur
2025-11-21 9:53 [PATCH 0/4] soc: qcom: llcc: Add support for Glymur SoC Pankaj Patil
` (2 preceding siblings ...)
2025-11-21 9:53 ` [PATCH 3/4] soc: qcom: llcc: Fix usecase id macro alignment Pankaj Patil
@ 2025-11-21 9:53 ` Pankaj Patil
2025-11-21 13:16 ` Konrad Dybcio
3 siblings, 1 reply; 10+ messages in thread
From: Pankaj Patil @ 2025-11-21 9:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Conor Dooley, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
sibi.sankar, rajendra.nayak
Add system cache table(SCT) and configs for Glymur SoC
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
drivers/soc/qcom/llcc-qcom.c | 207 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 13e174267294..1abfda7a58f2 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -182,6 +182,197 @@ enum llcc_reg_offset {
LLCC_TRP_WRS_CACHEABLE_EN,
};
+static const struct llcc_slice_config glymur_data[] = {
+ {
+ .usecase_id = LLCC_CPUSS,
+ .slice_id = 1,
+ .max_cap = 7680,
+ .priority = 1,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_VIDSC0,
+ .slice_id = 2,
+ .max_cap = 512,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_AUDIO,
+ .slice_id = 6,
+ .max_cap = 1024,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_VIDSC1,
+ .slice_id = 4,
+ .max_cap = 512,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_CMPT,
+ .slice_id = 10,
+ .max_cap = 7680,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_GPUHTW,
+ .slice_id = 11,
+ .max_cap = 512,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_GPU,
+ .slice_id = 9,
+ .max_cap = 7680,
+ .priority = 1,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .write_scid_en = true,
+ .write_scid_cacheable_en = true,
+ .stale_en = true,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_MMUHWT,
+ .slice_id = 18,
+ .max_cap = 768,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_AUDHW,
+ .slice_id = 22,
+ .max_cap = 1024,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_CVP,
+ .slice_id = 8,
+ .max_cap = 64,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_WRCACHE,
+ .slice_id = 31,
+ .max_cap = 1536,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_CMPTHCP,
+ .slice_id = 17,
+ .max_cap = 256,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_LCPDARE,
+ .slice_id = 30,
+ .max_cap = 768,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .alloc_oneway_en = true,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_AENPU,
+ .slice_id = 3,
+ .max_cap = 3072,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .cache_mode = 2,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_ISLAND1,
+ .slice_id = 12,
+ .max_cap = 5632,
+ .priority = 7,
+ .fixed_size = true,
+ .bonus_ways = 0x0,
+ .res_ways = 0x7FF,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_VIDVSP,
+ .slice_id = 28,
+ .max_cap = 256,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_OOBM_NS,
+ .slice_id = 5,
+ .max_cap = 512,
+ .priority = 1,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_CPUSS_OPP,
+ .slice_id = 32,
+ .max_cap = 0,
+ .fixed_size = true,
+ .bonus_ways = 0x0,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_PCIE_TCU,
+ .slice_id = 19,
+ .max_cap = 256,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_VIDSC_VSP1,
+ .slice_id = 29,
+ .max_cap = 256,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }
+};
+
static const struct llcc_slice_config ipq5424_data[] = {
{
.usecase_id = LLCC_CPUSS,
@@ -3872,6 +4063,16 @@ static const struct qcom_llcc_config kaanapali_cfg[] = {
},
};
+static const struct qcom_llcc_config glymur_cfg[] = {
+ {
+ .sct_data = glymur_data,
+ .size = ARRAY_SIZE(glymur_data),
+ .reg_offset = llcc_v6_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ .no_edac = true,
+ },
+};
+
static const struct qcom_llcc_config qcs615_cfg[] = {
{
.sct_data = qcs615_data,
@@ -4103,6 +4304,11 @@ static const struct qcom_sct_config kaanapali_cfgs = {
.num_config = ARRAY_SIZE(kaanapali_cfg),
};
+static const struct qcom_sct_config glymur_cfgs = {
+ .llcc_config = glymur_cfg,
+ .num_config = ARRAY_SIZE(glymur_cfg),
+};
+
static const struct qcom_sct_config qcs615_cfgs = {
.llcc_config = qcs615_cfg,
.num_config = ARRAY_SIZE(qcs615_cfg),
@@ -4941,6 +5147,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_llcc_of_match[] = {
+ { .compatible = "qcom,glymur-llcc", .data = &glymur_cfgs },
{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},
{ .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs},
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
2025-11-21 9:53 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block Pankaj Patil
@ 2025-11-21 10:35 ` Krzysztof Kozlowski
0 siblings, 0 replies; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-21 10:35 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Conor Dooley,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, sibi.sankar,
rajendra.nayak
On 21/11/2025 10:53, Pankaj Patil wrote:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,glymur-llcc
> + then:
> + properties:
> + reg:
> + items:
> + - description: LLCC0 base register region
> + - description: LLCC1 base register region
> + - description: LLCC2 base register region
> + - description: LLCC3 base register region
> + - description: LLCC4 base register region
> + - description: LLCC5 base register region
> + - description: LLCC6 base register region
> + - description: LLCC7 base register region
> + - description: LLCC8 base register region
> + - description: LLCC9 base register region
> + - description: LLCC10 base register region
> + - description: LLCC11 base register region
> + - description: LLCC broadcast base register region
> + - description: LLCC broadcast AND register region
Max is 10, so this is too many. You need to fix top-level constraints.
> + reg-names:
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] soc: qcom: llcc: Fix usecase id macro alignment
2025-11-21 9:53 ` [PATCH 3/4] soc: qcom: llcc: Fix usecase id macro alignment Pankaj Patil
@ 2025-11-21 10:36 ` Krzysztof Kozlowski
0 siblings, 0 replies; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-21 10:36 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Conor Dooley,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, sibi.sankar,
rajendra.nayak
On 21/11/2025 10:53, Pankaj Patil wrote:
> Fixed spacing for usecase id macro along the
What is exactly fixed?
> column length
Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
Cleanups go before new features/devices.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/4] soc: qcom: llcc: Enable additional usecase id for Glymur
2025-11-21 9:53 ` [PATCH 2/4] soc: qcom: llcc: Enable additional usecase id for Glymur Pankaj Patil
@ 2025-11-21 10:37 ` Krzysztof Kozlowski
2025-11-21 11:05 ` Pankaj Patil
0 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-21 10:37 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Conor Dooley,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, sibi.sankar,
rajendra.nayak
On 21/11/2025 10:53, Pankaj Patil wrote:
> Update the list of usecase id's to enable additional clients
> for Glymur SoC
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> include/linux/soc/qcom/llcc-qcom.h | 4 ++++
That's not a separate patch. We do not want defines just for defines.
You add defines because some code uses it, so there is a user. Where? It
must be in this patch, for all typical cases.
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 0287f9182c4d..8243ab3a12a8 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -74,13 +74,17 @@
> #define LLCC_CAMSRTIP 73
> #define LLCC_CAMRTRF 74
> #define LLCC_CAMSRTRF 75
> +#define LLCC_OOBM_NS 81
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/4] soc: qcom: llcc: Enable additional usecase id for Glymur
2025-11-21 10:37 ` Krzysztof Kozlowski
@ 2025-11-21 11:05 ` Pankaj Patil
0 siblings, 0 replies; 10+ messages in thread
From: Pankaj Patil @ 2025-11-21 11:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Conor Dooley,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, sibi.sankar,
rajendra.nayak
On 11/21/2025 4:07 PM, Krzysztof Kozlowski wrote:
> On 21/11/2025 10:53, Pankaj Patil wrote:
>> Update the list of usecase id's to enable additional clients
>> for Glymur SoC
>>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> include/linux/soc/qcom/llcc-qcom.h | 4 ++++
> That's not a separate patch. We do not want defines just for defines.
> You add defines because some code uses it, so there is a user. Where? It
> must be in this patch, for all typical cases.
Understood, will squash with driver changes where the defines are used
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
>> index 0287f9182c4d..8243ab3a12a8 100644
>> --- a/include/linux/soc/qcom/llcc-qcom.h
>> +++ b/include/linux/soc/qcom/llcc-qcom.h
>> @@ -74,13 +74,17 @@
>> #define LLCC_CAMSRTIP 73
>> #define LLCC_CAMRTRF 74
>> #define LLCC_CAMSRTRF 75
>> +#define LLCC_OOBM_NS 81
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] soc: qcom: llcc-qcom: Add support for Glymur
2025-11-21 9:53 ` [PATCH 4/4] soc: qcom: llcc-qcom: Add support for Glymur Pankaj Patil
@ 2025-11-21 13:16 ` Konrad Dybcio
0 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2025-11-21 13:16 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Conor Dooley,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, sibi.sankar,
rajendra.nayak
On 11/21/25 10:53 AM, Pankaj Patil wrote:
> Add system cache table(SCT) and configs for Glymur SoC
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
I have verified all the values here are correct
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-11-21 13:16 UTC | newest]
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2025-11-21 9:53 [PATCH 0/4] soc: qcom: llcc: Add support for Glymur SoC Pankaj Patil
2025-11-21 9:53 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block Pankaj Patil
2025-11-21 10:35 ` Krzysztof Kozlowski
2025-11-21 9:53 ` [PATCH 2/4] soc: qcom: llcc: Enable additional usecase id for Glymur Pankaj Patil
2025-11-21 10:37 ` Krzysztof Kozlowski
2025-11-21 11:05 ` Pankaj Patil
2025-11-21 9:53 ` [PATCH 3/4] soc: qcom: llcc: Fix usecase id macro alignment Pankaj Patil
2025-11-21 10:36 ` Krzysztof Kozlowski
2025-11-21 9:53 ` [PATCH 4/4] soc: qcom: llcc-qcom: Add support for Glymur Pankaj Patil
2025-11-21 13:16 ` Konrad Dybcio
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