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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: george.moussalem@outlook.com,
	Bjorn Andersson <andersson@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Luo Jie <quic_luoj@quicinc.com>, Lee Jones <lee@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support
Date: Fri, 2 May 2025 12:38:10 +0200	[thread overview]
Message-ID: <bd1ce180-1282-45f1-a893-5cc097eb6613@oss.qualcomm.com> (raw)
In-Reply-To: <20250502-ipq5018-cmn-pll-v1-3-27902c1c4071@outlook.com>

On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
> ethernet block. The CMN PLL to the ethernet block must be enabled first
> by setting a specific register in the TCSR area set in the device tree.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---

[...]

> +static inline int ipq_cmn_pll_eth_enable(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	unsigned int cmn_pll_offset;
> +	struct regmap *tcsr;
> +	int ret;
> +
> +	tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,cmn-pll-eth-enable",
> +						    1, &cmn_pll_offset);

So we have syscon_regmap_lookup_by_phandle_args() and
syscon_regmap_lookup_by_phandle_optional(), but we could also
use a syscon_regmap_lookup_by_phandle_args_optional() - could
you add that in drivers/mfd/syscon.c?

> +	if (IS_ERR(tcsr)) {
> +		ret = PTR_ERR(tcsr);
> +		/*
> +		 * continue if -ENODEV is returned as not all IPQ SoCs
> +		 * need to enable CMN PLL. If it's another error, return it.
> +		 */
> +		if (ret == -ENODEV)
> +			tcsr = NULL;
> +		else
> +			return ret;
> +	}
> +
> +	if (tcsr) {
> +		ret = regmap_update_bits(tcsr, cmn_pll_offset + TCSR_CMN_PLL_ETH,

I think it's better to just pass the exact register that we need,
instead of some loosely defined subregion - especially given the
structure likely will change across platforms

> +					 TCSR_CMN_PLL_ETH_ENABLE, TCSR_CMN_PLL_ETH_ENABLE);

regmap_set_bits()

> +		if (ret)
> +			return ret;

You can initialize ret to 0 and return ret below, unconditionally

> +	}
> +
> +	return 0;
> +}
> +
>  static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
>  	int ret;
>  
> +	ret = ipq_cmn_pll_eth_enable(pdev);
> +	if (ret)
> +		return dev_err_probe(dev, ret,
> +				     "Fail to enable CMN PLL to ethernet");

Fail*ed*

Konrad

  reply	other threads:[~2025-05-02 10:38 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-02 10:15 [PATCH 0/6] Add CMN PLL clock controller support for IPQ5018 George Moussalem via B4 Relay
2025-05-02 10:15 ` [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC George Moussalem via B4 Relay
2025-05-02 11:35   ` Rob Herring (Arm)
2025-05-02 14:17   ` Rob Herring
2025-05-02 16:14     ` George Moussalem
2025-05-04  1:49   ` Jie Luo
2025-05-04  7:03     ` George Moussalem
2025-05-05  2:55       ` Jie Luo
2025-05-02 10:15 ` [PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical George Moussalem via B4 Relay
2025-05-02 10:29   ` Konrad Dybcio
2025-05-02 12:45     ` George Moussalem
     [not found]     ` <b05d9351-cc79-4e60-a6e0-de2fe698098f@outlook.com>
2025-05-04  6:59       ` George Moussalem
2025-05-06  0:59         ` Konrad Dybcio
2025-05-02 10:15 ` [PATCH 3/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support George Moussalem via B4 Relay
2025-05-02 10:38   ` Konrad Dybcio [this message]
2025-05-02 13:04     ` George Moussalem
2025-05-02 10:15 ` [PATCH 4/6] dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018 George Moussalem via B4 Relay
2025-05-09 22:05   ` Rob Herring (Arm)
2025-05-02 10:15 ` [PATCH 5/6] arm64: dts: ipq5018: Add CMN PLL node George Moussalem via B4 Relay
2025-05-04  1:53   ` Jie Luo
2025-05-04  7:10     ` George Moussalem
2025-05-02 10:15 ` [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock George Moussalem via B4 Relay
2025-05-02 10:39   ` Konrad Dybcio
2025-05-02 14:45   ` Dmitry Baryshkov
2025-05-02 15:53     ` George Moussalem
2025-05-04  2:17       ` Jie Luo
2025-05-04  7:14         ` George Moussalem
2025-05-02 19:31 ` [PATCH 0/6] Add CMN PLL clock controller support for IPQ5018 Rob Herring (Arm)

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