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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bd4f4dea93dsm221177266b.38.2026.05.15.05.57.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2026 05:57:31 -0700 (PDT) Message-ID: Date: Fri, 15 May 2026 14:57:29 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 10/14] dt-bindings: media: qcom: Add CAMSS Offline Processing Engine (OPE) To: Loic Poulain Cc: Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Kees Cook , "Gustavo A. R. Silva" , Bryan O'Donoghue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devicetree@vger.kernel.org, laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com References: <20260427-camss-isp-ope-v2-0-f430e7485009@oss.qualcomm.com> <20260427-camss-isp-ope-v2-10-f430e7485009@oss.qualcomm.com> <0c6c9366-a190-4143-a0fb-2aff38ed8804@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=D7Z37PRj c=1 sm=1 tr=0 ts=6a07183d cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=MDVsdYFiAoUeNHFhHhoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE1MDEzMSBTYWx0ZWRfX55lOqVojELVP d/8Vo/xovDSKykJSuvaHZgL2lqemp4Qr8Op3gNpRZtBJVrYc62lVD/0+Kyt/p5T/e5ECa6AWxAe Ov67oxSa4JWOXjDjQKMiI5V23+U7rcXzDF2JwBV8QFRVSWnbyNFAUeMYACR6lZ8JLMDjiiV+qan fnEHDA6dKZmFd5iCJ8o7l7A6XEIP2OOdf8MqbMKDSW1Y1+v0VDzQty+24zMoRwnbvo/EDl2EjBC Ne1v+3glhsVkWCtkao8zSnhIgGNUjjstNHwdmYWHca35rOl0kBLYk4HP3yKAa1HwqayCWHxDUfE FOBxyoZtjzau1Tp0UaxtjcSl6Iv/oz3d59M0UbtILMTTTYTW1pKlICXO7hG5bq2h7wkDU5PcstI iQvAaaOTzCutGUu98J1UgWeFa2iheHGo3LzIwKwnAe+C10W6O0vkAR4VYZG6p70H5TjOdnx3QGO JM/aeR1/z2oYEY6yiFA== X-Proofpoint-ORIG-GUID: WK_vEV6oRIOfO8wSufy77NBD9QyWbrHp X-Proofpoint-GUID: WK_vEV6oRIOfO8wSufy77NBD9QyWbrHp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-15_03,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605150131 On 5/5/26 3:16 PM, Loic Poulain wrote: > On Tue, Apr 28, 2026 at 12:16 PM Konrad Dybcio > wrote: >> >> On 4/27/26 10:33 PM, Loic Poulain wrote: >>> On Mon, Apr 27, 2026 at 4:22 PM Konrad Dybcio >>> wrote: >>>> >>>> On 4/27/26 2:43 PM, Loic Poulain wrote: >>>>> Add Devicetree binding documentation for the Qualcomm Camera Subsystem >>>>> Offline Processing Engine (OPE) found on platforms such as Agatti. >>>>> The OPE is a memory-to-memory image processing block which operates >>>>> on frames read from and written back to system memory. >>>>> >>>>> Signed-off-by: Loic Poulain >>>>> --- >>>> >>>> [...] >>>> >>>>> + clocks = <&gcc GCC_CAMSS_OPE_CLK>, >>>>> + <&gcc GCC_CAMSS_OPE_AHB_CLK>, >>>>> + <&gcc GCC_CAMSS_NRT_AXI_CLK>; >>>> >>>> Should the two AXI clocks be aggregated by camss-top instead? >>>> >>>> Otherwise we run the risk of the OPE driver setting a rate of A >>>> and another sub-device setting a rate of B >>> >>> On qcm2290, OPE appears to be the only consumer of the NRT AXI clock, >>> while the capture path (VFE/TFE) relies on the RT AXI clock. That >>> said, this may not always be the case and these clocks (AXI / NRT‑AXI >>> / RT‑AXI) seem like they could reasonably be managed at the >>> camss-bus/top level. >>> >>> The open question is how the NRT AXI clock should be enabled when >>> required? enabling them unconditionally (similar to other camss PM >>> clocks), introducing a dedicated CAMSS top‑level interface for voting, >>> or leveraging an existing framework to handle this? >> >> So, interconnect, or some internal, smaller version of it? > > Downstream, there is a CPAS driver that handles these clocks in > conjunction with the internal CAMNOC block. Dmitry also mentioned the > existing icc_clock mechanism, but we likely need to investigate this > further to support proper dynamic scaling of the required clocks. > However, I don’t plan to address this as part of the current series, > as it would significantly increase its scope. > > I believe the current approach is acceptable for now because: > - This NRT clock is required by this specific sub-block, but not by > all CAMSS sub-blocks (unlike, for example, camss-ahb), so referencing > it makes sense here. > - At the moment, the OPE only enables this clock without setting its > rate (i.e., it uses the default), so this should not conflict with > introducing a more complete scaling framework later. > > Does this sound good? Depends how you're going to want to tackle this debt in the future. If you go through the icc framework, you'll end up needing to alter the DT If you bake in something internal to the camss family, say camss_foo_bar_request_bandwidth(u32 val), you may get it done without that. But I don't know what practical challenges that will entail Konrad