Re: [PATCH v2 1/3] dt-bindings: clock: altr,agilex72-clkmgr: add Agilex72 clock manager

["Chiam, Evon" <evon.chiam@altera.com>]

Hi Krzysztof,

Please find my reply inline.

On 9/30/2026 6:48 PM, Krzysztof Kozlowski wrote:
> On Tue, Sep 29, 2026 at 05:38:12PM +0800, evon.chiam@altera.com wrote:
>> From: "Chiam, Evon" <evon.chiam@altera.com>
>>
>> The Agilex72 clock manager exposes four register regions: the clock
>> manager itself plus three general purpose PLLs.
>>
>> Add the schema and the clock ID header that consumers index.
>>
>> Signed-off-by: Chiam, Evon <evon.chiam@altera.com>
>> ---
> 
> Where is patch 3/3?
> 
Patch 3/3 was sent here:
https://lore.kernel.org/all/d6a2a5026a6a00d0b7ecfae76ff299f5b9752686.1790661931.git.evon.chiam@altera.com/

I accidentally sent it with different threading metadata, so it did not 
appear in the same v2 thread. Sorry for the confusion. I will resend the 
full series as v3 with proper threading.

>> Changes in v2:
>> - Subject: dropped the redundant "binding" suffix.
>> - Reworded the commit message.
>> - Dropped the external fixed-clock nodes from the example; they are not
>>    relevant to this binding.
>> - Dropped AGILEX72_NUM_CLKS from the clock ID header; it is not part of
>>    the binding. The driver derives it instead.
>> - Added the clocks and clock-names properties for the four external
>>    reference clocks, made them required, and used them in the example.
> 
> ...
> 
>> +  clocks:
>> +    items:
>> +      - description: External oscillator input
>> +      - description: Internal oscillator divided by 2
>> +      - description: Internal oscillator divided by 10
>> +      - description: FPGA fabric to SoC free running clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: osc1
> 
> osc
> 
>> +      - const: cb-intosc-div2-clk
> 
> Drop -clk
> 
Will fix in v3 to remove the redundant -clk suffixes.
>> +      - const: cb-intosc-div10-clk
> 
> Names are odd, seems like you put here source clock names, not the
> actual logical names of the inputs.
> 
Will address in v3 by using logical input names.
>> +      - const: f2s-free-clk
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - clocks
>> +  - clock-names
>> +  - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    clkmgr: clock-controller@915c000 {
> 
> and drop unused label.
> 
Will remove the unused label in v3.
> Best regards,
> Krzysztof

Thanks and best regards,
Evon