From mboxrd@z Thu Jan  1 00:00:00 1970
From: Shawn Lin <shawn.lin@rock-chips.com>
Subject: Re: [PATCH v2 1/2] Documentation: bindings: add dt doc for Rockchip
 PCIe controller
Date: Sun, 12 Jun 2016 09:34:56 +0800
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To: Doug Anderson <dianders@chromium.org>, Shawn Lin <shawn.lin@rock-chips.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de>, Marc Zyngier <marc.zyngier@arm.com>, linux-pci@vger.kernel.org, Wenrui Li <wenrui.li@rock-chips.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>, Rob Herring <robh+dt@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>
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=E5=9C=A8 2016/6/10 12:01, Doug Anderson =E5=86=99=E9=81=93:
> Shawn,
>
> On Wed, Jun 8, 2016 at 1:05 AM, Shawn Lin <shawn.lin@rock-chips.com> =
wrote:
>> +pcie0: pcie@f8000000 {
>> +       compatible =3D "rockchip,rk3399-pcie";
>> +       #address-cells =3D <3>;
>> +       #size-cells =3D <2>;
>> +       clocks =3D <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
>> +                <&cru PCLK_PCIE>;
>> +       clock-names =3D "aclk", "aclk-perf",
>> +                     "hclk";
>
> Code also requires a "pm" clock.
>
>> +       bus-range =3D <0x0 0x1>;
>> +       interrupts =3D <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50=
 IRQ_TYPE_LEVEL_HIGH>,
>> +                    <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> +       interrupt-names: "sys", "legacy", "client";
>
> Shouldn't be ":", should be "=3D".
>
>
>> +       assigned-clocks =3D <&cru SCLK_PCIEPHY_REF>;
>> +       assigned-clock-parents =3D <&cru SCLK_PCIEPHY_REF100M>;
>> +       assigned-clock-rates =3D <100000000>;
>> +       ep-gpios =3D <&gpio3 13 GPIO_ACTIVE_HIGH>;
>> +       ranges =3D < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x6000=
00
>> +                  0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000=
 >;
>
> nit: I don't thin it's common to have spaces before/after the ">" and=
 "<".
> nit: Be consistent about 0 vs. 0x0 in ranges.
>
>
>> +       num-lanes =3D <4>;
>> +       reg =3D < 0x0 0xf8000000 0x0 0x2000000 >, < 0x0 0xfd000000 0=
x0 0x1000000 >;
>> +       reg-name =3D "axi-base", "apb-base";
>
> Should be "reg-names" (with an "s")
>
>
>> +       resets =3D <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, <&cru=
 SRST_PCIE_MGMT>,
>> +                <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>=
;
>> +       reset-names =3D "core", "mgmt", "mgmt-sticky", "pipe";
>
> You have 5 resets but 4 reset names.  That doesn't seem right.  Code
> shows you only getting 4, so presumably you need to remove the
> SRST_PCIEPHY one.

Thanks for catching these above as I forgot to rework the this sample.

>
>
> -Doug
>
> _______________________________________________
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>


--=20
Best Regards
Shawn Lin