From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D2E83A8FFF; Tue, 20 Jan 2026 12:30:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768912219; cv=none; b=iF/QwP1L0uLXuhDraj2QJzK0sggkgL53zo/FBITp7b43bU8iNueFWoGSJX2nBzgwZ5xNqLg35gwINEith84i8VX3Cmg9YCmjtLFIpTCsOSrraxZfib+GAAv+Hu+hTvrLhb9Nd1J1JVG0cZHahaUHDUDWDUpn8Kp9Rw3wfNWw6GY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768912219; c=relaxed/simple; bh=xBs/MwE3PqTwhLqA7Q8KYvDEWAqMaIzPGGNLMJe5yOA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=IH/Fj1ripwKK8TIR/zd+PX+t7vNmhsUdCHTXp22yj6DvM3hl0qeSPaVWoRaHxQThmhTL+QvWAaLrJLCRjLzfAEInqXYThooOtlI0ODMV9niwsRymeXKqwXVu5IRYXg5qNfFHRGbQyWFME4lgRcBw/X0Fzrw9qj3sXvLYBZkgc70= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UT5s/7+B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UT5s/7+B" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3F0E9C16AAE; Tue, 20 Jan 2026 12:30:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768912218; bh=xBs/MwE3PqTwhLqA7Q8KYvDEWAqMaIzPGGNLMJe5yOA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=UT5s/7+BdcwGYFN3XpVEaTOIu6U/5Yt59Xdx3BihSaQASRv3Nbi3R+Hzha1frQuie f0QYK3CWvcsbZ/ESYSA7S9+1+qx0qV+4UORENMQtqnX/L58dzxnSXozdPjMJ1YPJqj Vypp4jUjbaUGlGre1lkLHhiawj8WWX792PWtxa1ntu04QNraGDnj3elr36LIwNpHrO rORK/koYljxFrZ1E7M0ZRq7CB3R6FTq7b0WCVa2+gILOSEC72IVa1vQWV1WBgCW71b 702zAA1Ojhe00ox/lIzxazo93HTkSD2RyDYqk3MAU61156mRciN8JUtztJWNW53iDm s8Jd/3CEpTz8A== Message-ID: Date: Tue, 20 Jan 2026 13:30:13 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: display: msm: qcm2290-mdss: Fix iommus property To: Sumit Garg Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, akhilpo@oss.qualcomm.com, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, robin.clark@oss.qualcomm.com, lumag@kernel.org, loic.poulain@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg References: <20260116062004.237356-1-sumit.garg@kernel.org> <20260116062004.237356-2-sumit.garg@kernel.org> <20260116-transparent-dexterous-nightingale-c029cb@quoll> <6020af2a-5baa-4594-8cbc-bf7241f0128e@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 20/01/2026 13:16, Sumit Garg wrote: > >> >>> >>> There has been ongoing disscusion related to how stream ID associated >>> with different translation context can be represented in DT here [1]. >>> With that only the secure bank stream IDs can be properly represented. >>> >>> Here I just followed the approach taken by Adreno GPU bindings for the >>> iommus property [2]. >>> >>> [2] Documentation/devicetree/bindings/display/msm/gpu.yaml +82 >> >> Such justifications are pointless. What about commit msg which explains >> why this was added? What about entire public discussion happening with >> this patch? What about all previous revisions of that patch and >> discussions leading to this piece of code? So you just found few lines >> of code, ignored entire background and any other arguments, and copied >> it here. > > Looks like you are mixing other patch-set with this one. How different? You found some old code and use it as argument that you can do the same: "Here I just followed the approach taken by Adreno GPU bindings for the" so how I am mixing patchsets in my response above? > >> >> That's the approach - I found a piece of some buggy code, so I can do >> the same. >> >> Again, we discussed it 2-3 months ago for the same patch and I gave >> exactly same reason why this patch is incomplete. > > Sorry you are just mixing different discussions here. I am trying to fix How am I mixing? Exactly same approach was posted for other SoC. I gave same comments. Same comments apply here. > the SMMU stream IDs for Agatti SoC which listed secure bank stream IDs > incorrectly. You explain what you did, but you did not explain why or how I mixed anything. > > And this is the first version of this patch only for DT bindings fix for > Agatti, there are no prior discussions I had on this aspect upstream. I did not say you had discussions before. I said exactly same problems were being solved and I give here and there exactly the same feedback. Best regards, Krzysztof