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[79.54.235.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37895665ba0sm5821843f8f.48.2024.09.09.04.40.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Sep 2024 04:40:38 -0700 (PDT) Message-ID: Date: Mon, 9 Sep 2024 13:39:26 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/9] dt-bindings: iio: dac: ad3552r: add io-backend property To: Jonathan Cameron Cc: Lars-Peter Clausen , Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, David Lechner References: <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-0-87d669674c00@baylibre.com> <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-1-87d669674c00@baylibre.com> <20240908132925.331c5175@jic23-huawei> Content-Language: en-US From: Angelo Dureghello In-Reply-To: <20240908132925.331c5175@jic23-huawei> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 08/09/24 2:29 PM, Jonathan Cameron wrote: > On Thu, 05 Sep 2024 17:17:31 +0200 > Angelo Dureghello wrote: > >> From: Angelo Dureghello >> >> There is a version AXI DAC IP block (for FPGAs) that provides >> a physical bus for AD3552R and similar chips. This can be used >> instead of a typical SPI controller to be able to use the chip >> in ways that typical SPI controllers are not capable of. >> >> The binding is modified so that either the device is a SPI >> peripheral or it uses an io-backend. >> >> Signed-off-by: Angelo Dureghello >> >> required: >> - compatible >> - - reg >> - - spi-max-frequency > Sort of feels like both reg and spi-max-frequency > are valid things to specify. This specific backend IP generates a fixed non-configurable clock frequency, so i don't think the spi-max-frequency is needed. > Maybe we have an excellent IP and dodgy wiring so want > to clamp the frequency (long term - don't need to support > in the driver today). > > Maybe we have an axi_dac IP that supports multiple > front end devices? So maybe just keep reg? yes, this is what i am wondering now too, i simplified with just one frontend node, are multimple frontends (and so reg property) needed ? >> >> additionalProperties: false >> >> @@ -238,4 +254,26 @@ examples: >> }; >> }; >> }; >> + >> + - | >> + backend: axi_dac@44a70000 { >> + compatible = "adi,axi-dac-ad3552r"; >> + reg = <0x44a70000 0x1000>; >> + dmas = <&dac_tx_dma 0>; >> + dma-names = "tx"; >> + #io-backend-cells = <0>; >> + clocks = <&ref_clk>; >> + dac { >> + compatible = "adi,ad3552r"; >> + reset-gpios = <&gpio0 92 1>; >> + io-backends = <&backend>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + channel@0 { >> + reg = <0>; >> + adi,output-range-microvolt = <(-10000000) (10000000)>; >> + }; >> + }; >> + }; >> + >> ... >> Regards, -- ,,, Angelo Dureghello :: :. BayLibre -runtime team- Developer :`___: `____: