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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id o14-20020a2e9b4e000000b002d2e63069a8sm81831ljj.63.2024.02.28.09.37.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Feb 2024 09:37:33 -0800 (PST) Message-ID: Date: Wed, 28 Feb 2024 18:37:30 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 1/7] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings Content-Language: en-US To: Rob Herring , Sibi Sankar Cc: sudeep.holla@arm.com, cristian.marussi@arm.com, andersson@kernel.org, jassisinghbrar@gmail.com, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_rgottimu@quicinc.com, quic_kshivnan@quicinc.com, conor+dt@kernel.org References: <20240117173458.2312669-1-quic_sibis@quicinc.com> <20240117173458.2312669-2-quic_sibis@quicinc.com> <20240130171240.GA1929440-robh@kernel.org> From: Konrad Dybcio In-Reply-To: <20240130171240.GA1929440-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/30/24 18:12, Rob Herring wrote: > On Wed, Jan 17, 2024 at 11:04:52PM +0530, Sibi Sankar wrote: >> Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox >> controller. >> >> Signed-off-by: Sibi Sankar >> --- >> .../bindings/mailbox/qcom,cpucp-mbox.yaml | 51 +++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> >> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> new file mode 100644 >> index 000000000000..2617e5555acb >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> @@ -0,0 +1,51 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller >> + >> +maintainers: >> + - Sibi Sankar >> + >> +description: >> + The CPUSS Control Processor (CPUCP) mailbox controller enables communication >> + between AP and CPUCP by acting as a doorbell between them. >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - qcom,x1e80100-cpucp-mbox >> + - const: qcom,cpucp-mbox > > A generic fallback implies multiple devices use the same unchanged > block. That seems doubtful given you have not defined any others and > given Konrad's comments. FWIW Sibi and I talked about this a bit off-list, this mailbox is apparently new and has nothing to do with what I mentioned on other platforms Konrad