From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABDFE1369B6; Thu, 22 Aug 2024 06:29:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724308158; cv=none; b=OCZ/JD9oxtWTXzFatDOVi19hMistEPkrG3eXOuf72YB7pH2q+ojDLmRFTviODR5wxxVC66t3xxp/91l7xgVhszPQpSeSqXCAwsTjjd/LOnQiVtsFDPXkGXQoRaKnNN1jymNU8b2PI/VQJHujBBz4cg6Y3f3sGCVC9+miwv5tQLQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724308158; c=relaxed/simple; bh=dxIr/zqhDUwIpOVfWk4NZpFnujX6cxAfQAQhph03ztA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Omov5pndAbYCChXULP/NJxolUjhgHjmOPMuomEhOgBObHzsQtuopF03RqZZt3e7bx7fwHYVqUhN47LYufBF5eY7eBFQlexXlormO+l6tMpL3Gqn7+Z6MRI1nye/YeBjqo/c33qsqtZ3YiUwf20Hh9D2Lr2BsU+6OfcOGeA1z87o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EyUPGA68; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EyUPGA68" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11FF8C4AF09; Thu, 22 Aug 2024 06:29:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724308158; bh=dxIr/zqhDUwIpOVfWk4NZpFnujX6cxAfQAQhph03ztA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=EyUPGA68VoOh0x8sUndjLFgOAJ7tHwG09dQtO/DtIG1z6iKJdfM89ZggczTLaE94Z pIa7r9OLjMgdxhNi+DaraWTjRoHjLbWJTE3Dwh4ixzBpLpRI9xTf16vPno12TkJ8Ql gMx6wwl6ZngWnT5Ml4ZLQxNBr2mGJqwftdlQHElB51cd2RPqLE2r7faLveljbqxSSj vt2k1YjYz9a/HHcTRUMWG/YWrxOek5X5ZRftdY8FWZDT8od3w96MVVBEpp0IUxgyN8 Bf5Bh2CUbaHmHdCCH+ix41CTw4S/GsyOehqXb0uWvy0FU07pYYKCjFlcCl8tQAO9yx eKRqxZ+GSVFYQ== Message-ID: Date: Thu, 22 Aug 2024 08:29:10 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC To: Jie Luo Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_kkumarcs@quicinc.com, quic_suruchia@quicinc.com, quic_pavir@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, bartosz.golaszewski@linaro.org, srinivas.kandagatla@linaro.org References: <20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com> <20240820-qcom_ipq_cmnpll-v2-1-b000dd335280@quicinc.com> <51198961-2e09-4d0e-8bf3-907c81597724@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 21/08/2024 18:08, Jie Luo wrote: > > > On 8/21/2024 4:33 PM, Krzysztof Kozlowski wrote: >> On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: >>> The CMN PLL controller provides clocks to networking hardware blocks >>> on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, >>> and produces output clocks at fixed rates. These output rates are >>> predetermined, and are unrelated to the input clock rate. The output >>> clocks are supplied to the Ethernet hardware such as PPE (packet >>> process engine) and the externally connected switch or PHY device. >>> >>> Signed-off-by: Luo Jie >>> --- >>> .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ >>> include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ >>> 2 files changed, 85 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >>> new file mode 100644 >>> index 000000000000..7ad04b58a698 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >>> @@ -0,0 +1,70 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm CMN PLL Clock Controller on IPQ SoC >>> + >>> +maintainers: >>> + - Bjorn Andersson >>> + - Luo Jie >>> + >>> +description: >>> + The CMN PLL clock controller expects a reference input clock. >> >> You did not explain what is CMN. Is this some sort of acronym? > > CMN is short form for 'common'. Since it is referred to as 'CMN' > PLL in the hardware programming guides, we wanted the driver name > to include it as well. The description can be updated as below to > clarify the name and purpose of this hardware block. Hope this is > fine. > > "The CMN PLL clock controller expects a reference input clock > from the on-board Wi-Fi, and supplies a number of fixed rate > output clocks to the Ethernet devices including PPE (packet > process engine) and the connected switch or PHY device. The > CMN (or 'common') PLL's only function is to enable clocks to > Ethernet hardware used with the IPQ SoC and does not include > any other function." So the block is called "CMN" in hardware programming guide, without any explanation of the acronym? Best regards, Krzysztof