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[61.92.221.177]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9f49f80sm10152790b3a.117.2025.07.14.08.59.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jul 2025 08:59:42 -0700 (PDT) Message-ID: Date: Mon, 14 Jul 2025 23:59:36 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND v7 00/21] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support To: Will Deacon Cc: Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter , Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Krzysztof Kozlowski References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> Content-Language: en-US From: Nick Chan In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Will Deacon 於 2025/7/14 夜晚11:12 寫道: > On Mon, Jun 16, 2025 at 09:31:49AM +0800, Nick Chan wrote: >> This series adds support for the CPU PMU in the older Apple A7-A11, T2 >> SoCs. These PMUs may have a different event layout, less counters, or >> deliver their interrupts via IRQ instead of a FIQ. Since some of those >> older SoCs support 32-bit EL0, counting for 32-bit EL0 also need to >> be enabled by the driver where applicable. >> >> Patch 1 adds the DT bindings. >> Patch 2-7 prepares the driver to allow adding support for those >> older SoCs. > Modulo my nits, the patches look alright to this point... > >> Patch 8-12 adds support for the older SoCs. > ... but I'm not sure if anybody actually cares about these older SoCs > and, even if they do, what the state of the rest of Linux is on those > parts. I recall horror stories about the OS being quietly migrated > between CPUs with incompatible features, at which point I think we have > to question whether we actually care about supporting this hardware. The "horror" story you mentioned is about Apple A10/A10X/T2, which has a big little switcher integrated into the cpufreq block, so when the cpufreq driver switch between states in the same way as on other SoCs, on these SoCs that would silently cause a CPU migration. There is only one incompatible feature that I am aware of which is 32-bit EL0 support. However, since the CPUs in these SoCs does not support 4K pages anyways in practice this is not an issue for as long as CONFIG_EXPERT is disabled. > > On the other hand, if it all works swimmingly and it's just the PMU > driver that needs updating, then I could get on board with it. As mentioned above, it does all work fine when CONFIG_EXPERT is not enabled, and if it is enabled, then 32-bit process may crash with illegal instruction but everything else will still works fine. > > Will > Nick Chan