From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C65E7C0015E for ; Fri, 28 Jul 2023 06:58:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233277AbjG1G6a (ORCPT ); Fri, 28 Jul 2023 02:58:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232825AbjG1G63 (ORCPT ); Fri, 28 Jul 2023 02:58:29 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D73701FFA for ; Thu, 27 Jul 2023 23:58:28 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-314417861b9so1659866f8f.0 for ; Thu, 27 Jul 2023 23:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690527507; x=1691132307; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=iftaUnOVi0WItO5ujzoJ74yz/u7rI0zj1tXOnX70SiU=; b=gnTkAf4jKjqvw3D0gLbYc3BVQKNvCUIJXKHHBHEq5LLEy0xMC3Wye8gy53UmiEdyMH 8+zOqQyvd/pbLBQzM7VNhGyzRqc4JR7Mh1JZxilfeSoi8SozTrYIlKq1Tqx9PonbEJyQ nONzdxsCgAOgKvwaaNxQiMxaQz7NBTDJIpyNH+ZHdNOcwEGdwGVXorKtnvFiPHBpcEnn vbP+EtzBk5GXe8jDMCtcHt5/KZM+5yI33wsU6Lm3GKl6hpvtbF4DfQB+SJ5dV1qqnTZE FRStCo0U+/8FjqHemMjf6WtuFhUXremL6VRQ2wIocxkHgCjtVisvXdQDDxFneQ6p3KP0 NO4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690527507; x=1691132307; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=iftaUnOVi0WItO5ujzoJ74yz/u7rI0zj1tXOnX70SiU=; b=OBn4ZBXsihsQ43KvdQo3SDa8h1nhd5TapXOTdF8oLkrTVDD3CbD5txsJgCSasoSRC4 3W4u6YmKhA8VAnCHAESDMWbXR5+Tc1XXUwuVlFH8RniKsgyeGKR+CGprIBHOnQfnxk6X dhcLT9+EsBVzivw3383fyFlyN5AaKgwFUsHYC4mw0wNgiXtUOTTD57Y/ZejF6lWW++ZK 5PgQaMtad80Sayulu8yIkXIIf9oC5F/byI8OuE7Mm+MtIQvRDkrwv4KuuKeE3O+pHbu+ EHLBRqBGRci4jIbuM7h91+8bvi5W+q1KOyhQQJkrjzqjevL0Ko5CAccDc2DIGTSZ1ANV hc0Q== X-Gm-Message-State: ABy/qLYbRDmpKYpex/LBg2i4ojdZ6prfc1bNCUwu+LbK+V9QjCA6po6b gXTC4v/MDZUiSMQofY+N1Anl0Q== X-Google-Smtp-Source: APBJJlH74MhrNj52K2JQ3OFV5R+EOUknys3ZEpt8lbO1nGVe2KfuEUWoAPNijHM7Yry2nXJj/++DrQ== X-Received: by 2002:a5d:5589:0:b0:317:6ef1:7939 with SMTP id i9-20020a5d5589000000b003176ef17939mr1030919wrv.23.1690527507368; Thu, 27 Jul 2023 23:58:27 -0700 (PDT) Received: from [192.168.1.20] ([178.197.223.104]) by smtp.gmail.com with ESMTPSA id o3-20020adfe803000000b003143b7449ffsm345862wrm.25.2023.07.27.23.58.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jul 2023 23:58:26 -0700 (PDT) Message-ID: Date: Fri, 28 Jul 2023 08:58:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Content-Language: en-US To: Eric Lin Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, zong.li@sifive.com, greentime.hu@sifive.com, vincent.chen@sifive.com References: <20230720135125.21240-1-eric.lin@sifive.com> <20230720135125.21240-2-eric.lin@sifive.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 28/07/2023 08:01, Eric Lin wrote: > Hi Krzysztof, > > On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski > wrote: >> >> On 20/07/2023 15:51, Eric Lin wrote: >>> This add YAML DT binding documentation for SiFive Private L2 >>> cache controller >>> >>> Signed-off-by: Eric Lin >>> Reviewed-by: Zong Li >>> Reviewed-by: Nick Hu >> >> >> ... >> >>> +properties: >>> + compatible: >>> + items: >>> + - const: sifive,pl2cache1 >> >> I still have doubts that it is not used in any SoC. This is what you >> said last time: "is not part of any SoC." >> If not part of any SoC, then where is it? Why are you adding it to the >> kernel? >> > > Sorry for the late reply. I didn't describe it clearly last time. > Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. > The pl2cache0 is used in unmatched board SoC. The pl2cache1 is > utilized in our internal FPGA platform for evaluation; it's our core > IP. And why do you add bindings for some internal FPGA IP block which does not interface with any SW? Best regards, Krzysztof