From: <Conor.Dooley@microchip.com>
To: <jassisinghbrar@gmail.com>
Cc: <palmer@dabbelt.com>, <robh+dt@kernel.org>,
<Damien.LeMoal@wdc.com>, <aou@eecs.berkeley.edu>,
<paul.walmsley@sifive.com>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <j.neuschaefer@gmx.net>,
<Lewis.Hanly@microchip.com>, <Cyril.Jean@microchip.com>,
<Daire.McNamara@microchip.com>, <Atish.Patra@wdc.com>,
<Anup.Patel@wdc.com>, <david.abdurachmanov@gmail.com>
Subject: Re: [PATCH v4 0/5] Add support for the PolarFire SoC system controller
Date: Fri, 2 Apr 2021 12:08:35 +0000 [thread overview]
Message-ID: <bec1f254-12e2-0613-6233-43a7090e6643@microchip.com> (raw)
In-Reply-To: <CABb+yY2s+ovT4Dhbsy4Mjn2EtgEwYdezhmUcL3H8GWCdaO2bPA@mail.gmail.com>
On 31/03/2021 00:54, Jassi Brar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Tue, Mar 30, 2021 at 6:06 AM <Conor.Dooley@microchip.com> wrote:
>
>>>> create mode 100644
>>>> Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
>>>> create mode 100644 drivers/mailbox/mailbox-mpfs.c
>>>> create mode 100644 drivers/soc/microchip/Kconfig
>>>> create mode 100644 drivers/soc/microchip/Makefile
>>>> create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c
>>>> create mode 100644 include/soc/microchip/mpfs.h
>>> The only problem I see here is that patch #3 (the driver for the system
>>> controller) comes before patch #4 (the DT bindings for that driver).
>>> That
>>> triggers a checkpatch warning. I can just reorder it, but it would be
>>> great to
>>> have some reviews from the DT and mailbox people. If not I'll try and
>>> find
>>> some time to take a closer look.
>> I've had a fair bit of back and forth with Rob about the dt bindings,
>> hopefully this version he happy with - think all of his concerns have
>> now been addressed. Haven't heard anything from Jassi Brar on the device
>> tree side however
>this version
this should read "the next version" not "this version"
> Nowhere is explained how the controller works, and the bindings seem
> trivial, so I have no concern.
>
> -j
We have documentation for the services provided by the system controller
here, and I'll provide this link with the cover letter when I submit v5
(direct download link to a pdf):
https://www.microsemi.com/document-portal/doc_download/1244853-ug0905-polarfire-soc-fpga-system-services-user-guide
Several of the services have drivers completed/in progress, but I have
been holding off on submitting them until this series was accepted since
they belong in a bunch of different subsystems.
Conor.
prev parent reply other threads:[~2021-04-02 12:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 11:34 [PATCH v4 0/5] Add support for the PolarFire SoC system controller conor.dooley
2021-03-30 4:17 ` Palmer Dabbelt
2021-03-30 11:06 ` Conor.Dooley
2021-03-30 23:54 ` Jassi Brar
2021-04-02 12:08 ` Conor.Dooley [this message]
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