From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
Dmitry Osipenko <digetx@gmail.com>,
krzysztof.kozlowski@canonical.com, robh+dt@kernel.org,
thierry.reding@gmail.com, jonathanh@nvidia.com,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org
Cc: vdumpa@nvidia.com, Snikam@nvidia.com
Subject: Re: [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward
Date: Thu, 31 Mar 2022 22:49:38 +0300 [thread overview]
Message-ID: <bf8bee92-0d0e-453b-5ff1-1829a4406fd1@collabora.com> (raw)
In-Reply-To: <06174428-edb1-6478-1b2c-ede83c4bfa87@nvidia.com>
On 3/30/22 14:22, Ashish Mhetre wrote:
...
>>> If we are to remove this callback then how to handle unknown interrupt
>>> channel error?
>>
>> Create a common helper function that returns ID of the raised channel or
>> errorno if not bits are set.
>>
> So something like this:
>
> int status_to_channel(const struct tegra_mc *mc, u32 status,
> unsigned int *mc_channel)
> {
> if ((status & mc->soc->ch_intmask) == 0)
> return -EINVAL;
>
> *mc_channel = __ffs((status & mc->soc->ch_intmask) >>
> mc->soc->status_reg_chan_shift);
>
> return 0;
> }
>
> Correct?
Yes
>>> Also we want to handle interrupts on one channel at a time and then
>>> clear it from status register. There can be interrupts on multiple
>>> channel. So multiple bits from status will be set. Hence it will be
>>> hard to parameterize shift such that it gives appropriate channel.
>>> So I think current approach is fine. Please correct me if I am wrong
>>> somewhere.
>>
>> You may do the following:
>>
>> 1. find the first channel bit set in the status reg
>> 2. handle that channel
>> 3. clear only the handled status bit, don't clear the other bits
>> 4. return from interrupt
>>
>> If there are other bits set, then interrupt handler will fire again and
>> next channel will be handled.
>
> For clearing status bit after handling, we can retrieve channel bit by
> something like this:
>
> ch_bit = BIT(*mc_channel) << mc->soc->status_reg_chan_shift;
>
> Correct?
Yes
Perhaps using FIELD_PREP() and alike helpers could make it look nice in
the code.
next prev parent reply other threads:[~2022-03-31 19:49 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-16 9:25 [Patch v5 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-16 9:25 ` [Patch v5 1/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-19 15:42 ` Dmitry Osipenko
2022-03-22 16:13 ` Ashish Mhetre
2022-03-25 4:50 ` Ashish Mhetre
2022-03-29 23:48 ` Dmitry Osipenko
2022-03-30 5:07 ` Ashish Mhetre
2022-03-20 12:31 ` Krzysztof Kozlowski
2022-03-22 18:04 ` Ashish Mhetre
2022-03-22 18:24 ` Krzysztof Kozlowski
2022-03-16 9:25 ` [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-19 15:50 ` Dmitry Osipenko
2022-03-19 16:19 ` Dmitry Osipenko
2022-03-22 17:51 ` Ashish Mhetre
2022-03-22 16:48 ` Ashish Mhetre
2022-03-19 15:59 ` Dmitry Osipenko
2022-03-22 17:23 ` Ashish Mhetre
2022-03-29 23:51 ` Dmitry Osipenko
2022-03-30 5:02 ` Ashish Mhetre
2022-03-19 16:14 ` Dmitry Osipenko
2022-03-22 17:34 ` Ashish Mhetre
2022-03-30 0:01 ` Dmitry Osipenko
2022-03-30 10:16 ` Ashish Mhetre
2022-03-30 10:36 ` Dmitry Osipenko
2022-03-30 11:22 ` Ashish Mhetre
2022-03-31 19:49 ` Dmitry Osipenko [this message]
2022-03-31 21:55 ` Ashish Mhetre
2022-03-20 12:53 ` Dmitry Osipenko
2022-03-23 8:36 ` Ashish Mhetre
2022-03-30 0:06 ` Dmitry Osipenko
2022-03-30 9:03 ` Ashish Mhetre
2022-03-30 10:19 ` Dmitry Osipenko
2022-03-30 10:34 ` Ashish Mhetre
2022-03-16 9:25 ` [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-19 15:42 ` Dmitry Osipenko
2022-03-20 2:13 ` Rob Herring
2022-03-20 12:42 ` Krzysztof Kozlowski
2022-03-22 18:12 ` Ashish Mhetre
2022-03-22 18:42 ` Krzysztof Kozlowski
2022-03-16 9:25 ` [Patch v5 4/4] arm64: tegra: Add memory controller channels Ashish Mhetre
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