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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: -iWsUombjrAHwuVYBpoKjcKeWdeYN7CS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI5MDE0NSBTYWx0ZWRfX2mSq6rz2TY58 INFR/nVOb/tEmi6TUs7LXZ4CFmsofYXmp5ChHYQ4oirRbYQjjzUGYc0cXTjmKOZCm/MhcdKtVBy UFzvY5gcNBxl+2QHl71IfdbMwp0QvG7/qHWSJmXKFD9pHafXVrq3Nenu0By0PyrcT1oisihmWDu hrFPL7RKivl3qoGN1sbHg4fg/LAP8Z/C0HMV2BBgLeKk1uCxUuoKMQcrOrFJAU24njGdE72daXi jljrG/h8PULeI0XM8M7a9vhZ/zypnMDLvxDJBmns4IeZMmio9hDvn9m92eZOaWunzpATvhK93RS DHawAMTBp5Um5qW0rhjmPgZe50+puYsbCa1H8E7tkh452S2MwomXzZDO563rzLwyMOQHRUAeYcp bSbOhW9eA5xGhNzHPQ/WdyHorK2rOMnekVzOp5y7Q2nqjJ4J1ocbMUHmHgEHKclTBTQM4/ZDBYc ThdN/YiwdcC4rBFEp8Q== X-Proofpoint-GUID: -iWsUombjrAHwuVYBpoKjcKeWdeYN7CS X-Proofpoint-Spam-Info: AW1haW4tMjYwODI5MDE0NSBTYWx0ZWRfXw829raXVBqjp 8oKedMETVgPpnjUjWsDGnh5+HZTW+uti2mVDnMNFCTOIh85oJWhLibT8jQTtSqQ+nejxfAX6ZIG KRR4XaznKLtujpOcDd2s1LqSjDgFo3A= X-Authority-Analysis: v=2.4 cv=a5kAM0SF c=1 sm=1 tr=0 ts=6a930d53 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=PZ14JaS8AzYbITig/tPzRA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=UqCG9HQmAAAA:8 a=0nupcxNY4bLKEn-PqUgA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-29_04,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608290145 On 8/25/2026 4:12 PM, George Moussalem via B4 Relay wrote: > From: George Moussalem > > Flatten usb controller nodes and update to using latest bindings and > flattened driver approach. > > This SoC has two USB controllers of which the USB3 node had a ref clock > populated in the DWC3 child node. Add property to the USB3 node only to > select UTMI as reference clock for the DWC3 core to calculate the right > values for the period and frame length adjustment. > > Signed-off-by: George Moussalem [...] > > - interrupts = , > + interrupts = , > + , > ; > - interrupt-names = "pwr_event", > + interrupt-names = "dwc_usb3", > + "pwr_event", > "qusb2_phy"; > You are adding pwr_event irq here. Do mention that in the commit message or send this particular interrupt addition as a separate patch. > resets = <&gcc GCC_USB1_BCR>; > - status = "disabled"; > > - dwc_1: usb@7000000 { > - compatible = "snps,dwc3"; > - reg = <0x0 0x07000000 0x0 0xcd00>; > - interrupts = ; > - phys = <&qusb_phy_1>; > - phy-names = "usb2-phy"; > - tx-fifo-resize; > - snps,is-utmi-l1-suspend; > - snps,hird-threshold = /bits/ 8 <0x0>; > - snps,dis_u2_susphy_quirk; > - snps,dis_u3_susphy_quirk; > - dr_mode = "host"; > - }; > + phys = <&qusb_phy_1>; > + phy-names = "usb2-phy"; > + > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + dr_mode = "host"; > + If this is HS only, do we need to add "qcom,select-utmi-as-pipe-clk" ? [...] > + usb3: usb@8a00000 { > + compatible = "qcom,ipq6018-dwc3", "qcom,snps-dwc3"; > + reg = <0x0 0x08a00000 0x0 0xfc100>; > > clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, > - <&gcc GCC_USB0_MASTER_CLK>, > - <&gcc GCC_USB0_SLEEP_CLK>, > - <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > clock-names = "cfg_noc", > - "core", > - "sleep", > - "mock_utmi"; > + "core", > + "sleep", > + "mock_utmi"; > > assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, > <&gcc GCC_USB0_MASTER_CLK>, > @@ -692,32 +686,31 @@ usb3: usb@8af8800 { > <133330000>, > <24000000>; > > - interrupts = , > + interrupts = , > + , > , > ; > - interrupt-names = "pwr_event", > + interrupt-names = "dwc_usb3", > + "pwr_event", > "qusb2_phy", > "ss_phy_irq"; Same comment as above. > > resets = <&gcc GCC_USB0_BCR>; > - status = "disabled"; > > - dwc_0: usb@8a00000 { > - compatible = "snps,dwc3"; > - reg = <0x0 0x08a00000 0x0 0xcd00>; > - interrupts = ; > - phys = <&qusb_phy_0>, <&ssphy_0>; > - phy-names = "usb2-phy", "usb3-phy"; > - clocks = <&xo>; > - clock-names = "ref"; > - tx-fifo-resize; > - snps,parkmode-disable-ss-quirk; > - snps,is-utmi-l1-suspend; > - snps,hird-threshold = /bits/ 8 <0x0>; > - snps,dis_u2_susphy_quirk; > - snps,dis_u3_susphy_quirk; > - dr_mode = "host"; > - }; > + phys = <&qusb_phy_0>, <&ssphy_0>; > + phy-names = "usb2-phy", "usb3-phy"; > + > + qcom,select-utmi-as-ref-clk; > + > + tx-fifo-resize; > + snps,parkmode-disable-ss-quirk; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + dr_mode = "host"; This controller is DRD capable. Please move this dr_mode property to DTS file. Regards, Krishna,