From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
devicetree@vger.kernel.org,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: Re: [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin
Date: Thu, 18 Apr 2024 11:51:16 +0200 [thread overview]
Message-ID: <bfd6aa32-a28e-47a4-82c7-76c5dd99a44d@linaro.org> (raw)
In-Reply-To: <hi7vzqm5ebypzs6m6bw64ghgfwsdzuaxy65jpah37iw5ww7fku@n3c5sucic27i>
On 18.04.2024 1:43 AM, Dmitry Baryshkov wrote:
> On Wed, Apr 17, 2024 at 10:02:55PM +0200, Konrad Dybcio wrote:
>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>> abstracted through SMEM, instead of being directly available in a fuse.
>>
>> Add support for SMEM-based speed binning, which includes getting
>> "feature code" and "product code" from said source and parsing them
>> to form something that lets us match OPPs against.
>>
>> Due to the product code being ignored in the context of Adreno on
>> production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]
>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
>> @@ -6,6 +6,8 @@
>> * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
>> */
>>
>> +#include <linux/soc/qcom/socinfo.h>
>> +
>
> Stray leftover?
Looks like
[...]
>> +
>> +#ifdef CONFIG_QCOM_SMEM
>
> Please extract to a separate function and put the function under ifdef
> (providing a stub otherwise). Having #ifndefs inside funciton body is
> frowned upon.
Hm, this looked quite sparse and straightforward, but I can do that.
[...]
>> +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */
>> +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0)
>> +#define ADRENO_SKU_ID(fcode) (SOCINFO_PC_UNKNOWN << 16 | fcode)
>
> If we got rid of PCode matching, is there a need to actually use
> SOCINFO_PC_UNKNOWN here? Or just 0 would be fine?
The IDs need to stay constant for mesa
I used the define here to:
a) define the SKU_ID structure so that it's clear what it's comprised of
b) make it easy to add back Pcode in case it becomes useful with future SoCs
c) avoid mistakes - PC_UNKNOWN happens to be zero, but that's a lucky
coincidence
We don't *match* based on PCODE, but still need to construct the ID properly
Another option would be to pass the real pcode and add some sort of
"pcode_invalid" property that if found would ignore this part of the
SKU_ID in mesa, but that sounds overly and unnecessarily complex.
Konrad
Konrad
next prev parent reply other threads:[~2024-04-18 9:51 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-17 20:02 [PATCH v2 0/7] Add SMEM-based speedbin matching Konrad Dybcio
2024-04-17 20:02 ` [PATCH v2 1/7] soc: qcom: Move some socinfo defines to the header Konrad Dybcio
2024-04-17 20:02 ` [PATCH v2 2/7] soc: qcom: smem: Add a feature code getter Konrad Dybcio
2024-04-17 23:39 ` Dmitry Baryshkov
2024-04-18 9:53 ` Konrad Dybcio
2024-04-18 11:06 ` Dmitry Baryshkov
2024-05-28 21:06 ` Bjorn Andersson
2024-04-17 20:02 ` [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin Konrad Dybcio
2024-04-17 23:43 ` Dmitry Baryshkov
2024-04-18 9:51 ` Konrad Dybcio [this message]
2024-04-18 11:07 ` Dmitry Baryshkov
2024-04-18 11:31 ` Konrad Dybcio
2024-04-18 11:48 ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 4/7] drm/msm/adreno: Add speedbin data for SM8550 / A740 Konrad Dybcio
2024-04-17 23:44 ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 5/7] drm/msm/adreno: Define A530 speed bins explicitly Konrad Dybcio
2024-04-17 23:44 ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 6/7] drm/msm/adreno: Redo the speedbin assignment Konrad Dybcio
2024-04-17 23:49 ` Dmitry Baryshkov
2024-04-18 9:57 ` Konrad Dybcio
2024-04-18 11:29 ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 7/7] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Konrad Dybcio
2024-04-17 23:49 ` Dmitry Baryshkov
-- strict thread matches above, loose matches on Subject: below --
2024-06-05 20:10 [PATCH v2 0/7] Add SMEM-based speedbin matching Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin Konrad Dybcio
2024-06-25 17:20 ` Rob Clark
2024-06-25 17:41 ` Konrad Dybcio
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