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([2a01:e0a:982:cbb0:1a7d:7b36:3842:9bc3]) by smtp.gmail.com with ESMTPSA id h6-20020a05600c350600b0040e86fbd772sm2663887wmq.38.2024.01.25.05.41.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jan 2024 05:41:18 -0800 (PST) Message-ID: Date: Thu, 25 Jan 2024 14:41:18 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 5/6] arm64: dts: qcom: sm8550: describe all PCI MSI interrupts Content-Language: en-US, fr To: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> <20240125130626.390850-5-krzysztof.kozlowski@linaro.org> Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro Developer Services In-Reply-To: <20240125130626.390850-5-krzysztof.kozlowski@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 25/01/2024 14:06, Krzysztof Kozlowski wrote: > Each group of MSI interrupts is mapped to the separate host interrupt. > Describe each of interrupts in the device tree for PCIe hosts. Only > boot tested on hardware. > > Signed-off-by: Krzysztof Kozlowski > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++---- > 1 file changed, 20 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index ee1ba5a8c8fc..80e31fb21055 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1713,8 +1713,16 @@ pcie0: pcie@1c00000 { > linux,pci-domain = <0>; > num-lanes = <2>; > > - interrupts = ; > - interrupt-names = "msi"; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "msi0", "msi1", "msi2", "msi3", > + "msi4", "msi5", "msi6", "msi7"; > > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > @@ -1804,8 +1812,16 @@ pcie1: pcie@1c08000 { > linux,pci-domain = <1>; > num-lanes = <2>; > > - interrupts = ; > - interrupt-names = "msi"; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "msi0", "msi1", "msi2", "msi3", > + "msi4", "msi5", "msi6", "msi7"; > > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; 230: 22 0 0 0 0 0 0 0 PCI-MSI 134742016 Edge nvme0q0 232: 0 0 0 0 0 0 0 0 PCI-MSI 134742017 Edge nvme0q1 233: 1 0 0 0 0 0 0 0 PCI-MSI 134742018 Edge nvme0q2 234: 0 0 0 0 0 0 0 0 PCI-MSI 134742019 Edge nvme0q3 235: 1 0 0 0 0 0 0 0 PCI-MSI 134742020 Edge nvme0q4 236: 1 0 0 0 0 0 0 0 PCI-MSI 134742021 Edge nvme0q5 237: 23 0 0 0 0 0 0 0 PCI-MSI 134742022 Edge nvme0q6 238: 18 0 0 0 0 0 0 0 PCI-MSI 134742023 Edge nvme0q7 239: 0 0 0 0 0 0 0 0 PCI-MSI 134742024 Edge nvme0q8 258: 4 0 0 0 0 0 0 0 PCI-MSI 524288 Edge bhi 259: 5 0 0 0 0 0 0 0 PCI-MSI 524289 Edge mhi 260: 33 0 0 0 0 0 0 0 PCI-MSI 524290 Edge mhi 261: 3 0 0 0 0 0 0 0 PCI-MSI 524291 Edge ce0 262: 2 0 0 0 0 0 0 0 PCI-MSI 524292 Edge ce1 263: 41 0 0 0 0 0 0 0 PCI-MSI 524293 Edge ce2 264: 28 0 0 0 0 0 0 0 PCI-MSI 524294 Edge ce3 265: 0 0 0 0 0 0 0 0 PCI-MSI 524295 Edge ce5 266: 0 0 0 0 0 0 0 0 PCI-MSI 524296 Edge DP_EXT_IRQ 267: 0 0 0 0 0 0 0 0 PCI-MSI 524297 Edge DP_EXT_IRQ 268: 0 0 0 0 0 0 0 0 PCI-MSI 524298 Edge DP_EXT_IRQ 269: 0 0 0 0 0 0 0 0 PCI-MSI 524299 Edge DP_EXT_IRQ 270: 0 0 0 0 0 0 0 0 PCI-MSI 524300 Edge DP_EXT_IRQ 271: 0 0 0 0 0 0 0 0 PCI-MSI 524301 Edge DP_EXT_IRQ 272: 0 0 0 0 0 0 0 0 PCI-MSI 524302 Edge DP_EXT_IRQ Tested-by: Neil Armstrong # on SM8550-HDK 235: 4 0 0 0 0 0 0 0 PCI-MSI 524288 Edge bhi 236: 5 0 0 0 0 0 0 0 PCI-MSI 524289 Edge mhi 237: 33 0 0 0 0 0 0 0 PCI-MSI 524290 Edge mhi 238: 3 0 0 0 0 0 0 0 PCI-MSI 524291 Edge ce0 239: 2 0 0 0 0 0 0 0 PCI-MSI 524292 Edge ce1 240: 40 0 0 0 0 0 0 0 PCI-MSI 524293 Edge ce2 241: 29 0 0 0 0 0 0 0 PCI-MSI 524294 Edge ce3 242: 0 0 0 0 0 0 0 0 PCI-MSI 524295 Edge ce5 243: 0 0 0 0 0 0 0 0 PCI-MSI 524296 Edge DP_EXT_IRQ 244: 0 0 0 0 0 0 0 0 PCI-MSI 524297 Edge DP_EXT_IRQ 245: 0 0 0 0 0 0 0 0 PCI-MSI 524298 Edge DP_EXT_IRQ 246: 0 0 0 0 0 0 0 0 PCI-MSI 524299 Edge DP_EXT_IRQ 247: 0 0 0 0 0 0 0 0 PCI-MSI 524300 Edge DP_EXT_IRQ 248: 0 0 0 0 0 0 0 0 PCI-MSI 524301 Edge DP_EXT_IRQ 249: 0 0 0 0 0 0 0 0 PCI-MSI 524302 Edge DP_EXT_IRQ Tested-by: Neil Armstrong # on SM8550-QRD