From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E52F18AE2; Sat, 14 Dec 2024 10:13:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734171182; cv=none; b=Wz+crNl9KVzySgMaZvhYM7MxWzYLu2rCEns4AxlZu1jMeZ8kXufYY+paLjQoW7pm2lGBpg4b0mU5zG1i/tbvmqg84WZl2yu9z2kcxW8/K9SE3S+3iknWGRRKPu2iN+CrGzr+kJi/32yWwZbnBwmHIkCRBI3iNGgzthJuDxH7+Fc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734171182; c=relaxed/simple; bh=B4w7qyzubxMMydQEqp4vY3XoKkUYi/sW0XSUiYIB5GU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=sBbnvnQ6RTvADq5YysDFpXkjY7p2Vzm8q0qxgYYP6FJBPLGr9C3uNJYVdNP5nniTktzSwC/81IANjc7ZyZmeG0af9i+OZLU6UTHZNa9i0Hr35LQFBFobBKOVAw5wm7xXt+99gZc7Xt90082DZfyNB3XjLpg92Xe5Ls8najgwkk8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k64zMY3s; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k64zMY3s" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BE134C4CED1; Sat, 14 Dec 2024 10:12:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734171181; bh=B4w7qyzubxMMydQEqp4vY3XoKkUYi/sW0XSUiYIB5GU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=k64zMY3sXhjFqj8VWoHKVF0VfjCyE8haQyPK0AOsMGKc+HhyEiekPiy+/nBZAbut5 Z749auXM7u84JTN5l8Zrr+nls5mmHzxscTfI1fsOERBPeRfe8zz1UoaOsnvp82s4hH yvoTnb9xR1P5L1GnwFTNSIwOPySI3Kuu1WlAv2zE6L2GhCjR3N7o/bVU+gEbRMvHkt agXz3YeAgPCx/dpboWMg71cWoBsyBQxfoHqy6wxmSxTdkves24inTjZN5vUofZAn4F 20sVH855IJ88fi0L8B1f2Zt7rR+aMzM0FeaOtE0L8c7cZ23rSWSzm0POVFRFr/9qUv shjxm62HsuaAQ== Message-ID: Date: Sat, 14 Dec 2024 11:12:58 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/8] arm64: dts: morello: Add support for soc dts To: Vincenzo Frascino , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sudeep Holla , Rob Herring References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> <20241213163221.3626261-5-vincenzo.frascino@arm.com> Content-Language: en-US From: Krzysztof Kozlowski Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 13/12/2024 17:32, Vincenzo Frascino wrote: > The Morello architecture is an experimental extension to Armv8.2-A, > which extends the AArch64 state with the principles proposed in > version 7 of the Capability Hardware Enhanced RISC Instructions > (CHERI) ISA. > > Introduce Morello SoC dts. So Morello is an architecture, not a board or platform? You cannot have both... > > Cc: Sudeep Holla > Cc: Rob Herring > Signed-off-by: Vincenzo Frascino > --- > arch/arm64/boot/dts/arm/morello-soc.dts | 267 ++++++++++++++++++++++++ > 1 file changed, 267 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts > > diff --git a/arch/arm64/boot/dts/arm/morello-soc.dts b/arch/arm64/boot/dts/arm/morello-soc.dts > new file mode 100644 > index 000000000000..3c5247121e4d > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/morello-soc.dts > @@ -0,0 +1,267 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. > + > + */ > + > +/dts-v1/; > +#include "morello.dtsi" > + > +/ { > + model = "Arm Morello System Development Platform"; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + secure-firmware@ff000000 { > + reg = <0 0xff000000 0 0x01000000>; > + no-map; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + cpu0: cpu0@0 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x0>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 0>; > + }; > + cpu1: cpu1@100 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x100>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 0>; > + }; > + cpu2: cpu2@10000 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x10000>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 1>; > + }; > + cpu3: cpu3@10100 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x10100>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 1>; > + }; > + }; > + > + /* The first bank of memory, memory map is actually provided by UEFI. */ > + memory@80000000 { > + device_type = "memory"; > + /* [0x80000000-0xffffffff] */ > + reg = <0x00000000 0x80000000 0x0 0x7F000000>; > + }; > + > + memory@8080000000 { > + device_type = "memory"; > + /* [0x8080000000-0x83f7ffffff] */ > + reg = <0x00000080 0x80000000 0x3 0x78000000>; > + }; > + > + smmu_pcie: iommu@4f400000 { This all is weird. MMIO nodes outside of soc, soc pieces defined in DTS instead of DTSI. Please look first how all other DTS and DTSI are done. Also carefully read DTS coding style. Best regards, Krzysztof