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Thu, 25 Jan 2024 04:35:56 -0800 (PST) Received: from [192.168.1.20] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b0040e39cbf2a4sm2451204wmq.42.2024.01.25.04.35.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jan 2024 04:35:56 -0800 (PST) Message-ID: Date: Thu, 25 Jan 2024 13:35:53 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to dedicated schema Content-Language: en-US To: Manivannan Sadhasivam , Rob Herring Cc: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> <20240108-dt-bindings-pci-qcom-split-v1-1-d541f05f4de0@linaro.org> <20240116144419.GA3856889-robh@kernel.org> <20240117063039.GA8708@thinkpad> From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 17/01/2024 07:30, Manivannan Sadhasivam wrote: >> >> How does a given SoC have 1 or 8 interrupts? I guess it is possible. A >> comment here would be helpful. >> > > No, this is due to kernel developers not able to find out the max MSI numbers > for each platforms out of the Qcom internal documentation. > > Let it be for now, I will try to fetch these numbers to make it accurate later. I'll complete the interrupts the binding and the DTS. Best regards, Krzysztof