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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b723d6f8c5bsm233306166b.20.2025.11.04.07.20.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Nov 2025 07:20:51 -0800 (PST) Message-ID: Date: Tue, 4 Nov 2025 16:20:49 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] power: reset: qcom-pon: Add support for WARM reset To: Loic Poulain , krzk+dt@kernel.org Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, conor+dt@kernel.org, sre@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org References: <20251103182006.1158383-1-loic.poulain@oss.qualcomm.com> <20251103182006.1158383-3-loic.poulain@oss.qualcomm.com> <740b9e7c-59bc-4a35-a268-526d92db372c@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: EuVJ9uF3-ZZ9xux-E3kB-IXVHbt37lMO X-Proofpoint-GUID: EuVJ9uF3-ZZ9xux-E3kB-IXVHbt37lMO X-Authority-Analysis: v=2.4 cv=b7O/I9Gx c=1 sm=1 tr=0 ts=690a19d6 cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=nsY2OikdMtLjWMwq5xoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA0MDEyOCBTYWx0ZWRfX6GIbfUvf0fHG laK9jYc4mvgc66ZqaV1VASX9BvzdZTqaSWjWrkFhz4LQ4B1+zcH6cKysnVFcDjwXrHHFmVaOeWK 3+qO0NmK+YhCNtvDhENlI99fCaT/4VwsLnZxwpXImvmaD9XjSZdCeYSmfghzeR7xkqh4KIJlJRL qOYCYJQQCrQCZx9ojPic17jTTfmjTLVV7JCf8Wl7pBPoaUrAlfI0POiAGFqL1qb0lcSG5Dat1Tr rJZJbDT0ftUuISG4HsXJdBrgt+ZGFiAsHZ3Sy9yjC0k8PpWRc4vIwbZlujN+2seP3R872nBGfQo QtVAsP9XlQgUGO1z/+TGqHg45cW0L9kGVqtTKcRQ3PGf4wzNKuIaTa0GawzgC2ehs+VGfuS6Y0L unC3p/FMgXmG4bs0Jt3xMWMaEqMTrw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-04_01,2025-11-03_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511040128 On 11/4/25 4:01 PM, Loic Poulain wrote: > Hi Konrad, Krzysztof, > > On Tue, Nov 4, 2025 at 12:50 PM Konrad Dybcio > wrote: >> >> On 11/3/25 7:20 PM, Loic Poulain wrote: >>> This mechanism can be used when firmware lacks proper warm-reset handling, >>> for example, when the PSCI SYSTEM_RESET2 function is not implemented. >>> It enables the warm reset functionality via the PMIC. >>> >>> This fallback is only enabled if qcom,warm-reset property is present. >>> >>> Signed-off-by: Loic Poulain >>> --- >>> drivers/power/reset/qcom-pon.c | 47 ++++++++++++++++++++++++++++++++++ >>> 1 file changed, 47 insertions(+) >>> >>> diff --git a/drivers/power/reset/qcom-pon.c b/drivers/power/reset/qcom-pon.c >>> index 7e108982a582..684e9fe9987d 100644 >>> --- a/drivers/power/reset/qcom-pon.c >>> +++ b/drivers/power/reset/qcom-pon.c >>> @@ -19,12 +19,20 @@ >>> >>> #define NO_REASON_SHIFT 0 >>> >>> +#define PON_SW_RESET_S2_CTL 0x62 >>> +#define PON_SW_RESET_S2_CTL_WARM_RST 0x01 >>> +#define PON_SW_RESET_S2_CTL2 0x63 >>> +#define PON_SW_RESET_S2_CTL2_RST_EN BIT(7) >>> +#define PON_SW_RESET_GO 0x64 >>> +#define PON_SW_RESET_GO_MAGIC 0xa5 >> >> Going back to msm8974 where the SPMI arbiter first showed up, these >> values are all seemingly valid, so I think we can drop the dt property. >> The restart reasons are set in stone too, and you can find more of them >> in the register description. > > Yes, but this should only apply when the platform firmware does not > support warm reset via PSCI, right? > Making it unconditional would override the PSCI implementation even > when warm reset is supported. > > The point is that psci_sys_reset() executes a cold reset if warm > reset isn’t available. Therefore, our PMIC reboot notifier must have a > higher priority than the PSCI handler. > > So maybe the alternative could be to introduce an additional reboot > handler in psci, with the lowest priority, so that warm reset can have > a chance to run either from the psci main reboot handler or from the > PMIC reboot handler before falling back to cold reset? > [PSCI-handler]->[other-handlers]->[PSCI-cold-reset-fallback-handler] This seems like a common enough problem, perhaps the framework could accept EOPNOTSUPP or similar and try to delegate further, coming back with a normal restart or so, if unsupported. Trying to make a special contract between qcom-pon and psci silently will be very fragile otherwise. >> That said, we're circumventing PS_HOLD this way - is that intended? > > Well, we don’t have direct control over PS_HOLD since it’s managed by > the firmware in our case. That’s why I considered using the PMIC > software reset as an effective way to achieve this warm reset. Hm, so is there no longer a way to assert it by writing to PMIC registers? >> And do we need to take any special care where there's more than one >> PMIC onboard to make sure that the SoC gets properly reset? > > Good point, this likely only matters if the other PMIC reboot handler > performs the same type of reset and their actions overlap. I think there used to be some logic in the older days where Linux would manually go over all PMICs with a PON and send a reset to them. Maybe that's too old for this platform though. Konrad > In that case, I may need to remove the mdelay from this handler. > Additionally, if we adopt the PSCI change discussed above, the system > will fall back to a cold reset when a PMIC-based reset isn’t possible.