From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20A8313C695; Fri, 21 Mar 2025 20:56:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742590595; cv=none; b=V13B6OtIXBdOqQ2m1msCeNr146atS5zuYuWg9SYgbuNJ04uHBS56AkktPYMOW3EBj458CEPG44bcvRrUyfm/EyrcDFFgfcbwyn7JVy7LcqM42inziHQcC5aPpKEmg2LpIx5eYQ/YlEn6jIpr5R8t/GiwMpY3S1uf7i4PpFkLtGk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742590595; c=relaxed/simple; bh=ec3+o488fphAO1T0qvJyJYNbwPmkpTwgA5JJPdJ8RSk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=IfTIV1bia3y/dBWV1pfdSZMpzLKK+DpQuO/6vTKpC5yXK2f5ftvb3VC5tI6N0KJBnnzYGXeYebns+sZNVjiSAZu6TfWCHLrwmpffhpz8TZ1OIvGiehNX9jZ41kC4pY7O+9hirQ/8qVb23skPMB2lmpgz72HLyjvyMyr+bwpklb8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hSxvE5IF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hSxvE5IF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 722F1C4CEE3; Fri, 21 Mar 2025 20:56:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742590593; bh=ec3+o488fphAO1T0qvJyJYNbwPmkpTwgA5JJPdJ8RSk=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=hSxvE5IFT7zH25ei6WnDtLU0sFcu9ydwmTx/UyDdgcSMVfBswrk1afZzc5DpFLFbt eE9E7i3FLDdIrIxRLT4B38SdoF+tqiHl1atfY8ac3VsWy7ITeheVHQQd07IXoMNo5f uDa/93Yu1+6egWKBC3unIsrulPiRd4UGCuaeeFFGvwzJHvg8DiYXKd3Zg331+IQMJs KlMp3z+6U/N1l/PM1onnLacgYR6L+HRCvDTOpiZtON4BGVzfFkRmkrYUPxo2a78EXL RThnvi5Kt6pr45BYn48+O+ibCWAup/EV3VZgPLwS+uv1qlpfQFR5jQMhSv/RanKkQW QeiJNQTCutkOA== Message-ID: Date: Fri, 21 Mar 2025 21:56:27 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 4/8] dt-bindings: timer: Add EcoNet HPT CPU Timer To: Caleb James DeLisle , linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu References: <20250321134633.2155141-1-cjd@cjdns.fr> <20250321134633.2155141-5-cjd@cjdns.fr> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 21/03/2025 14:46, Caleb James DeLisle wrote: > Add device tree binding documentation for the high-precision timer (HPT) > in the EcoNet EN751221 SoC. > > Signed-off-by: Caleb James DeLisle Previous patch was not tested, so was this one tested? > --- > .../bindings/timer/econet,timer-hpt.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml > > diff --git a/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml b/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml > new file mode 100644 > index 000000000000..8b7ff9bce947 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/econet,timer-hpt.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: EcoNet High Precision Timer (HPT) > + > +maintainers: > + - Calev James DeLisle > + > +description: | Do not need '|' unless you need to preserve formatting. > + The EcoNet High Precision Timer (HPT) is a timer peripheral found in various > + EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE > + count/compare registers and a per-CPU control register, with a single interrupt > + line using a percpu-devid interrupt mechanism. > + > +properties: > + compatible: > + const: econet,timer-hpt Soc components must have soc-based compatible and then filename matching whatever you use as fallback. > + > + reg: > + minItems: 1 > + maxItems: 2 No, list items instead. > + description: | > + Physical base address and size of the timer's register space. On 34Kc > + processors, a single region is used. On 1004Kc processors, two regions are > + used, one for each core. So different hardware, different compatible. That's why you need soc-based compatibles. Follow standard SoC upstreaming rules and examples. > + > + interrupts: > + maxItems: 1 > + description: | Do not need '|' unless you need to preserve formatting. > + The interrupt number for the timer. Drop, redundant. > This is a percpu-devid interrupt shared > + across CPUs. > + > + clocks: > + maxItems: 1 > + description: | > + A clock to get the frequency of the timer. Drop description, redundant > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + timer_hpt@1fbf0400 { No underscores Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Look how other SoCs are calling this. > + compatible = "econet,timer-hpt"; > + reg = <0x1fbf0400 0x100>; > + interrupt-parent = <&intc>; > + interrupts = <30>; > + clocks = <&hpt_clock>; > + }; > +... Best regards, Krzysztof