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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id t12-20020ac2548c000000b004efae490c51sm471679lfk.240.2023.06.09.02.07.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Jun 2023 02:07:19 -0700 (PDT) Message-ID: Date: Fri, 9 Jun 2023 11:07:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH] arm64: dts: qcom: ipq9574: enable the SPI NOR support in RDP433 Content-Language: en-US To: Kathiravan T , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230609081508.30982-1-quic_kathirav@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230609081508.30982-1-quic_kathirav@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 9.06.2023 10:15, Kathiravan T wrote: > RDP433 has the support for SPI NOR, add the support for it. > > Signed-off-by: Kathiravan T > --- > Note: This patch was part of initial submission > https://lore.kernel.org/linux-arm-msm/20230329053726.14860-1-quic_kathirav@quicinc.com/ > however this got missed in between, so sending it across again. > > arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > index 2b3ed8d351f7..31ee19112157 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > @@ -48,6 +48,20 @@ > }; > }; > > +&blsp1_spi0 { > + pinctrl-0 = <&spi_0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + flash@0 { > + compatible = "micron,n25q128a11", "jedec,spi-nor"; > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <1>; If you're not adding a partition table, you can drop the address- and size-cells properties, as they determine what the reg value of the child looks like. Konrad > + spi-max-frequency = <50000000>; > + }; > +}; > + > &sdhc_1 { > pinctrl-0 = <&sdc_default_state>; > pinctrl-names = "default"; > @@ -96,6 +110,13 @@ > bias-pull-down; > }; > }; > + > + spi_0_pins: spi-0-state { > + pins = "gpio11", "gpio12", "gpio13", "gpio14"; > + function = "blsp0_spi"; > + drive-strength = <8>; > + bias-disable; > + }; > }; > > &xo_board_clk {