From: Dinh Nguyen <dinguyen@kernel.org>
To: Alan Tull <atull@kernel.org>
Cc: Alan Tull <atull@opensource.altera.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Dinh Nguyen <dinguyen@opensource.altera.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges
Date: Fri, 6 Jan 2017 01:39:25 -0600 [thread overview]
Message-ID: <c1f0db0e-18ae-660f-2ff0-4489419fe838@kernel.org> (raw)
In-Reply-To: <CANk1AXRsrW1YHRPn4Rcv7Pu8jBUEcOmREOFYvvMV8D9eKLU-6g@mail.gmail.com>
On 01/05/2017 10:34 AM, Alan Tull wrote:
> On Thu, Jan 5, 2017 at 10:28 AM, Alan Tull <atull@kernel.org> wrote:
>> On Wed, Jan 4, 2017 at 6:21 PM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>>> From: Alan Tull <atull@opensource.altera.com>
>>>
>>> Add h2f and lwh2f bridges.
>>> Add base FPGA Region to support DT overlays for FPGA programming.
>>> Add l3regs.
>>>
>>> Signed-off-by: Alan Tull <atull@opensource.altera.com>
>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>> ---
>>> arch/arm/boot/dts/socfpga.dtsi | 31 +++++++++++++++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index de29172..dccc281 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>> @@ -93,6 +93,16 @@
>>> };
>>> };
>>>
>>> + base_fpga_region {
>>> + compatible = "fpga-region";
>>> + fpga-mgr = <&fpgamgr0>;
>>> + fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>;
>>
>> Hi Dinh,
>>
>> We want to get rid of the 'fpga-bridges' line.
>>
>>> +
>>> + #address-cells = <0x1>;
>>> + #size-cells = <0x1>;
>>> + ranges = <0 0xff200000 0x100000>;
>>
>> Should get rid of the ranges line here too. The 'fpga-bridges' and
>> 'ranges' line can be added in the overlay.
>>
>> Alan
>>
>>> + };
>>> +
>>> can0: can@ffc00000 {
>>> compatible = "bosch,d_can";
>>> reg = <0xffc00000 0x1000>;
>>> @@ -513,6 +523,22 @@
>>> };
>>> };
>>>
>>> + fpga_bridge0: fpga_bridge@ff400000 {
>>> + compatible = "altr,socfpga-lwhps2fpga-bridge";
>>> + reg = <0xff400000 0x100000>;
>>> + resets = <&rst LWHPS2FPGA_RESET>;
>>> + reset-names = "lwhps2fpga";
>
> The driver doesn't need 'reset-names' here or below for fpga_bridge1.
>
Ok, thanks for the review.
Dinh
next prev parent reply other threads:[~2017-01-06 7:39 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
[not found] ` <1483575694-29599-1-git-send-email-dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2017-01-05 0:21 ` [PATCH 01/12] ARM: dts: socfpga: enable GPIO and LEDs for Cyclone5 and Arria5 devkits Dinh Nguyen
2017-01-05 0:21 ` [PATCH 02/12] ARM: dts: socfpga: set desired i2c clock on " Dinh Nguyen
2017-01-05 0:21 ` [PATCH 03/12] ARM: dts: socfpga: Add Rohm DH2228FV DAC Dinh Nguyen
2017-01-05 0:21 ` [PATCH 04/12] ARM: dts: socfpga: enable CAN on Cyclone5 devkit Dinh Nguyen
2017-01-05 0:21 ` [PATCH 05/12] ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10 Dinh Nguyen
2017-01-05 0:21 ` [PATCH 06/12] ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit Dinh Nguyen
2017-01-05 0:21 ` [PATCH 07/12] ARM: dts: socfpga: add fpga-manager node for Arria10 Dinh Nguyen
2017-01-05 0:21 ` [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree " Dinh Nguyen
2017-01-05 8:55 ` Steffen Trumtrar
2017-01-05 11:42 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 09/12] ARM: dts: socfpga: fpga manager data is 32 bits Dinh Nguyen
2017-01-05 0:21 ` [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges Dinh Nguyen
2017-01-05 16:28 ` Alan Tull
[not found] ` <CANk1AXSbqohp73xHpp7e9-37d61ZB-dRAPAFc2eQGRYUnvB+0w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-01-05 16:34 ` Alan Tull
2017-01-06 7:39 ` Dinh Nguyen [this message]
2017-01-05 0:21 ` [PATCH 11/12] ARM: dts: socfpga: add fpga region support on Arria10 Dinh Nguyen
2017-01-05 0:21 ` [PATCH 12/12] ARM: dts: socfpga: add missing compatible string for SDRAM controller Dinh Nguyen
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