* [PATCH 1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
@ 2026-03-30 10:27 ` Hui Min Mina Chou
2026-03-30 13:01 ` Krzysztof Kozlowski
2026-03-30 10:27 ` [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations Hui Min Mina Chou
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Hui Min Mina Chou @ 2026-03-30 10:27 UTC (permalink / raw)
To: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc
Cc: tim609, alex749, az70021, Hui Min Mina Chou, charles
Andes cache driver is not only usable with the AX45MP CPU but can also be
applied to other CPU within Andes platform (such as A27L2).
To improve maintainability and support future SoCs, this patch performs a
comprehensive refactoring to move away from model-specific naming.
key changes include:
- replaced AX45MP-specific Kconfig and function names with generic "ANDES"
prefixes to support multiple CPU types
- updated all L2-related identifiers, structs, and prefixes to "LLC"
to accurately reflect its role as the system's last-level cache
- moved UCCTL* CSR definitions to <linux/soc/andes/csr.h>
- standardized L1D and LLC macro prefixes (ANDES_L1D_* and ANDES_LLC_*)
for better clarity
- renamed compatible strings from ax45mp-cache to generic llcache
- rename ax45mp_cache.c to andes_llcache.c
This is a structural refactoring; no functional behavior is changed.
Signed-off-by: charles <dminus@andestech.com>
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
arch/riscv/Kconfig.errata | 2 +-
drivers/cache/Kconfig | 6 +-
drivers/cache/Makefile | 2 +-
drivers/cache/andes_llcache.c | 224 ++++++++++++++++++++++++++++++++++
drivers/cache/ax45mp_cache.c | 217 --------------------------------
drivers/soc/renesas/Kconfig | 2 +-
include/linux/soc/andes/csr.h | 12 ++
7 files changed, 242 insertions(+), 223 deletions(-)
create mode 100644 drivers/cache/andes_llcache.c
delete mode 100644 drivers/cache/ax45mp_cache.c
create mode 100644 include/linux/soc/andes/csr.h
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 3c945d086c7d..e32f1563ce3a 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -1,7 +1,7 @@
menu "CPU errata selection"
config ERRATA_ANDES
- bool "Andes AX45MP errata"
+ bool "Andes errata"
depends on RISCV_ALTERNATIVE && RISCV_SBI
help
All Andes errata Kconfig depend on this Kconfig. Disabling
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1518449d47b5..78142189f45c 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -10,11 +10,11 @@ menuconfig CACHEMAINT_FOR_DMA
if CACHEMAINT_FOR_DMA
-config AX45MP_L2_CACHE
- bool "Andes Technology AX45MP L2 Cache controller"
+config ANDES_CACHE
+ bool "Andes platform CPUs Cache controller"
select RISCV_NONSTANDARD_CACHE_OPS
help
- Support for the L2 cache controller on Andes Technology AX45MP platforms.
+ Support for the L1 and LLC (last level cache) controller on Andes platform CPUs.
config SIFIVE_CCACHE
bool "Sifive Composable Cache controller"
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index b3362b15d6c1..4a218ad6cec0 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
+obj-$(CONFIG_ANDES_CACHE) += andes_llcache.o
obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o
diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
new file mode 100644
index 000000000000..d5e382f3c801
--- /dev/null
+++ b/drivers/cache/andes_llcache.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * non-coherent cache operations for Andes Platform CPUs.
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include <linux/cacheflush.h>
+#include <linux/cacheinfo.h>
+#include <linux/dma-direction.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/soc/andes/csr.h>
+
+#include <asm/dma-noncoherent.h>
+
+/* L1 D-cache operation encoding */
+#define ANDES_L1D_CCTL_VA_INVAL 0x0 /* Invalidate an L1D cacheline */
+#define ANDES_L1D_CCTL_VA_WB 0x1 /* Write-back an L1D cacheline */
+#define ANDES_L1D_CCTL_VA_WBINVAL 0x2 /* Flush an L1D cacheline */
+#define ANDES_L1D_CCTL_WBINVAL_ALL 0x6 /* Flush the entire L1D cache */
+
+/* LLC registers */
+#define ANDES_LLC_REG_CFG_OFFSET 0x0
+#define ANDES_LLC_REG_CTRL_OFFSET 0x8
+#define ANDES_LLC_REG_ASYNC_ERR_OFFSET 0x30
+#define ANDES_LLC_REG_ERR_OFFSET 0x38
+#define ANDES_LLC_REG_CCTL_CMD_OFFSET_C0 0x40
+#define ANDES_LLC_REG_CCTL_ACC_OFFSET_C0 0x48
+#define ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0 0x80
+
+/* LLC CCTL status encoding */
+#define ANDES_LLC_CCTL_STATUS_IDLE 0x0
+#define ANDES_LLC_CCTL_STATUS_RUNNING 0x1
+#define ANDES_LLC_CCTL_STATUS_ILLEGAL 0x2
+
+/* LLC CCTL status core 0 mask */
+#define ANDES_LLC_CCTL_STATUS_MASK_C0 GENMASK(3, 0)
+
+/* LLC operation encoding */
+#define ANDES_LLC_CCTL_PA_INVAL 0x8 /* Invalidate an LLC cacheline */
+#define ANDES_LLC_CCTL_PA_WB 0x9 /* Write-back an LLC cacheline */
+#define ANDES_LLC_CCTL_PA_WBINVAL 0xa /* Flush an LLC cacheline */
+#define ANDES_LLC_CCTL_WBINVAL_ALL 0x12 /* Flush the entire LLC cache */
+
+/* LLC CCTL registers and fields by core */
+#define ANDES_LLC_REG_PER_CORE_OFFSET 0x10
+#define ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET 0x4
+
+#define ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(n) \
+ (ANDES_LLC_REG_CCTL_CMD_OFFSET_C0 + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
+#define ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(n) \
+ (ANDES_LLC_REG_CCTL_ACC_OFFSET_C0 + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
+#define ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(n) \
+ (ANDES_LLC_CCTL_STATUS_MASK_C0 << ((n) * ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET))
+
+#define ANDES_CACHE_LINE_SIZE 64
+
+struct andes_priv {
+ void __iomem *llc_base;
+ u32 andes_cache_line_size;
+};
+
+static struct andes_priv andes_priv;
+
+/* LLC operations */
+static inline uint32_t andes_cpu_llc_get_cctl_status(void)
+{
+ return readl(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
+}
+
+static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
+ unsigned int l1_op, unsigned int llc_op)
+{
+ unsigned long line_size = andes_priv.andes_cache_line_size;
+ void __iomem *base = andes_priv.llc_base;
+ int mhartid = smp_processor_id();
+ unsigned long pa;
+
+ while (end > start) {
+ csr_write(CSR_UCCTLBEGINADDR, start);
+ csr_write(CSR_UCCTLCOMMAND, l1_op);
+
+ pa = virt_to_phys((void *)start);
+ writel(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
+ writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
+ while ((andes_cpu_llc_get_cctl_status() &
+ ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
+ ANDES_LLC_CCTL_STATUS_IDLE)
+ ;
+
+ start += line_size;
+ }
+}
+
+/* Write-back L1 and LLC entry */
+static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end)
+{
+ andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_WB,
+ ANDES_LLC_CCTL_PA_WB);
+}
+
+/* Invalidate the L1 and LLC entry */
+static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end)
+{
+ andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_INVAL,
+ ANDES_LLC_CCTL_PA_INVAL);
+}
+
+static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+ unsigned long start = (unsigned long)phys_to_virt(paddr);
+ unsigned long end = start + size;
+ unsigned long line_size;
+ unsigned long flags;
+
+ if (unlikely(start == end))
+ return;
+
+ line_size = andes_priv.andes_cache_line_size;
+
+ start = start & (~(line_size - 1));
+ end = ((end + line_size - 1) & (~(line_size - 1)));
+
+ local_irq_save(flags);
+
+ andes_cpu_dcache_inval_range(start, end);
+
+ local_irq_restore(flags);
+}
+
+static void andes_dma_cache_wback(phys_addr_t paddr, size_t size)
+{
+ unsigned long start = (unsigned long)phys_to_virt(paddr);
+ unsigned long end = start + size;
+ unsigned long line_size;
+ unsigned long flags;
+
+ if (unlikely(start == end))
+ return;
+
+ line_size = andes_priv.andes_cache_line_size;
+ start = start & (~(line_size - 1));
+ end = ((end + line_size - 1) & (~(line_size - 1)));
+ local_irq_save(flags);
+ andes_cpu_dcache_wb_range(start, end);
+ local_irq_restore(flags);
+}
+
+static void andes_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+ andes_dma_cache_wback(paddr, size);
+ andes_dma_cache_inv(paddr, size);
+}
+
+static int andes_get_llc_line_size(struct device_node *np)
+{
+ int ret;
+
+ ret = of_property_read_u32(np, "cache-line-size", &andes_priv.andes_cache_line_size);
+ if (ret) {
+ pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
+ return ret;
+ }
+
+ if (andes_priv.andes_cache_line_size != ANDES_CACHE_LINE_SIZE) {
+ pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
+ andes_priv.andes_cache_line_size);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct riscv_nonstd_cache_ops andes_cmo_ops __initconst = {
+ .wback = &andes_dma_cache_wback,
+ .inv = &andes_dma_cache_inv,
+ .wback_inv = &andes_dma_cache_wback_inv,
+};
+
+static const struct of_device_id andes_cache_ids[] = {
+ { .compatible = "andestech,llcache" },
+ { /* sentinel */ }
+};
+
+static int __init andes_cache_init(void)
+{
+ struct resource res;
+ int ret;
+
+ struct device_node *np __free(device_node) =
+ of_find_matching_node(NULL, andes_cache_ids);
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret)
+ return ret;
+
+ /*
+ * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size
+ * will be 0 for sure, so we can definitely rely on it. If
+ * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
+ * more so we just return success here and only if its being set we
+ * continue further in the probe path.
+ */
+ if (!riscv_cbom_block_size)
+ return 0;
+
+ andes_priv.llc_base = ioremap(res.start, resource_size(&res));
+ if (!andes_priv.llc_base)
+ return -ENOMEM;
+
+ ret = andes_get_llc_line_size(np);
+ if (ret) {
+ iounmap(andes_priv.llc_base);
+ return ret;
+ }
+
+ riscv_noncoherent_register_cache_ops(&andes_cmo_ops);
+
+ return 0;
+}
+early_initcall(andes_cache_init);
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
deleted file mode 100644
index 934c5087ec2b..000000000000
--- a/drivers/cache/ax45mp_cache.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * non-coherent cache functions for Andes AX45MP
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-#include <linux/cacheflush.h>
-#include <linux/cacheinfo.h>
-#include <linux/dma-direction.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-
-#include <asm/dma-noncoherent.h>
-
-/* L2 cache registers */
-#define AX45MP_L2C_REG_CTL_OFFSET 0x8
-
-#define AX45MP_L2C_REG_C0_CMD_OFFSET 0x40
-#define AX45MP_L2C_REG_C0_ACC_OFFSET 0x48
-#define AX45MP_L2C_REG_STATUS_OFFSET 0x80
-
-/* D-cache operation */
-#define AX45MP_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */
-#define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
-
-/* L2 CCTL status */
-#define AX45MP_CCTL_L2_STATUS_IDLE 0
-
-/* L2 CCTL status cores mask */
-#define AX45MP_CCTL_L2_STATUS_C0_MASK 0xf
-
-/* L2 cache operation */
-#define AX45MP_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */
-#define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
-
-#define AX45MP_L2C_REG_PER_CORE_OFFSET 0x10
-#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET 4
-
-#define AX45MP_L2C_REG_CN_CMD_OFFSET(n) \
- (AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
-#define AX45MP_L2C_REG_CN_ACC_OFFSET(n) \
- (AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
-#define AX45MP_CCTL_L2_STATUS_CN_MASK(n) \
- (AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET))
-
-#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b
-#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM 0x80c
-
-#define AX45MP_CACHE_LINE_SIZE 64
-
-struct ax45mp_priv {
- void __iomem *l2c_base;
- u32 ax45mp_cache_line_size;
-};
-
-static struct ax45mp_priv ax45mp_priv;
-
-/* L2 Cache operations */
-static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void)
-{
- return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET);
-}
-
-static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end,
- unsigned int l1_op, unsigned int l2_op)
-{
- unsigned long line_size = ax45mp_priv.ax45mp_cache_line_size;
- void __iomem *base = ax45mp_priv.l2c_base;
- int mhartid = smp_processor_id();
- unsigned long pa;
-
- while (end > start) {
- csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start);
- csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
-
- pa = virt_to_phys((void *)start);
- writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid));
- writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid));
- while ((ax45mp_cpu_l2c_get_cctl_status() &
- AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
- AX45MP_CCTL_L2_STATUS_IDLE)
- ;
-
- start += line_size;
- }
-}
-
-/* Write-back L1 and L2 cache entry */
-static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigned long end)
-{
- ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_WB,
- AX45MP_CCTL_L2_PA_WB);
-}
-
-/* Invalidate the L1 and L2 cache entry */
-static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsigned long end)
-{
- ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_INVAL,
- AX45MP_CCTL_L2_PA_INVAL);
-}
-
-static void ax45mp_dma_cache_inv(phys_addr_t paddr, size_t size)
-{
- unsigned long start = (unsigned long)phys_to_virt(paddr);
- unsigned long end = start + size;
- unsigned long line_size;
- unsigned long flags;
-
- if (unlikely(start == end))
- return;
-
- line_size = ax45mp_priv.ax45mp_cache_line_size;
-
- start = start & (~(line_size - 1));
- end = ((end + line_size - 1) & (~(line_size - 1)));
-
- local_irq_save(flags);
-
- ax45mp_cpu_dcache_inval_range(start, end);
-
- local_irq_restore(flags);
-}
-
-static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
-{
- unsigned long start = (unsigned long)phys_to_virt(paddr);
- unsigned long end = start + size;
- unsigned long line_size;
- unsigned long flags;
-
- if (unlikely(start == end))
- return;
-
- line_size = ax45mp_priv.ax45mp_cache_line_size;
- start = start & (~(line_size - 1));
- end = ((end + line_size - 1) & (~(line_size - 1)));
- local_irq_save(flags);
- ax45mp_cpu_dcache_wb_range(start, end);
- local_irq_restore(flags);
-}
-
-static void ax45mp_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
-{
- ax45mp_dma_cache_wback(paddr, size);
- ax45mp_dma_cache_inv(paddr, size);
-}
-
-static int ax45mp_get_l2_line_size(struct device_node *np)
-{
- int ret;
-
- ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_cache_line_size);
- if (ret) {
- pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
- return ret;
- }
-
- if (ax45mp_priv.ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) {
- pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
- ax45mp_priv.ax45mp_cache_line_size);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initdata = {
- .wback = &ax45mp_dma_cache_wback,
- .inv = &ax45mp_dma_cache_inv,
- .wback_inv = &ax45mp_dma_cache_wback_inv,
-};
-
-static const struct of_device_id ax45mp_cache_ids[] = {
- { .compatible = "andestech,ax45mp-cache" },
- { /* sentinel */ }
-};
-
-static int __init ax45mp_cache_init(void)
-{
- struct resource res;
- int ret;
-
- struct device_node *np __free(device_node) =
- of_find_matching_node(NULL, ax45mp_cache_ids);
- if (!of_device_is_available(np))
- return -ENODEV;
-
- ret = of_address_to_resource(np, 0, &res);
- if (ret)
- return ret;
-
- /*
- * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size
- * will be 0 for sure, so we can definitely rely on it. If
- * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
- * more so we just return success here and only if its being set we
- * continue further in the probe path.
- */
- if (!riscv_cbom_block_size)
- return 0;
-
- ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res));
- if (!ax45mp_priv.l2c_base)
- return -ENOMEM;
-
- ret = ax45mp_get_l2_line_size(np);
- if (ret) {
- iounmap(ax45mp_priv.l2c_base);
- return ret;
- }
-
- riscv_noncoherent_register_cache_ops(&ax45mp_cmo_ops);
-
- return 0;
-}
-early_initcall(ax45mp_cache_init);
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 1e50dc7c31cd..e0319c8236ee 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -447,7 +447,7 @@ config ARCH_R9A07G043
depends on !RISCV_ISA_ZICBOM
depends on RISCV_SBI
select ARCH_RZG2L
- select AX45MP_L2_CACHE
+ select ANDES_CACHE
select CACHEMAINT_FOR_DMA
select DMA_GLOBAL_POOL
select ERRATA_ANDES
diff --git a/include/linux/soc/andes/csr.h b/include/linux/soc/andes/csr.h
new file mode 100644
index 000000000000..3214b4b08a46
--- /dev/null
+++ b/include/linux/soc/andes/csr.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2026 Andes Technology Corporation.
+ */
+#ifndef __LINUX_SOC_ANDES_CSR_H
+#define __LINUX_SOC_ANDES_CSR_H
+
+/* User mode control registers */
+#define CSR_UCCTLBEGINADDR 0x80b
+#define CSR_UCCTLCOMMAND 0x80c
+
+#endif /* !__LINUX_SOC_ANDES_CSR_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support
2026-03-30 10:27 ` [PATCH 1/7] cache: ax45mp_cache: refactor cache driver for generic Andes " Hui Min Mina Chou
@ 2026-03-30 13:01 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-30 13:01 UTC (permalink / raw)
To: Hui Min Mina Chou, pjw, palmer, aou, alex, geert+renesas,
prabhakar.mahadev-lad.rj, magnus.damm, ben717, robh, krzk+dt,
conor+dt, jonathan.cameron, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc
Cc: tim609, alex749, az70021, charles
On 30/03/2026 12:27, Hui Min Mina Chou wrote:
> -
> -static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initdata = {
> - .wback = &ax45mp_dma_cache_wback,
> - .inv = &ax45mp_dma_cache_inv,
> - .wback_inv = &ax45mp_dma_cache_wback_inv,
> -};
> -
> -static const struct of_device_id ax45mp_cache_ids[] = {
> - { .compatible = "andestech,ax45mp-cache" },
NAK, actual ABI break.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 1/7] cache: ax45mp_cache: refactor cache driver for generic Andes " Hui Min Mina Chou
@ 2026-03-30 10:27 ` Hui Min Mina Chou
2026-03-30 13:02 ` Krzysztof Kozlowski
2026-03-30 10:27 ` [PATCH 3/7] cache: andes_llcache: improve performance of LLC operation Hui Min Mina Chou
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Hui Min Mina Chou @ 2026-03-30 10:27 UTC (permalink / raw)
To: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc
Cc: tim609, alex749, az70021, Hui Min Mina Chou
This patch cleans up the Andes LLC cache driver:
- improved error handling in andes_cache_init() by using goto labels
- updated andes_dma_cache_inv/wback() to check for !size instead of
start == end
- cache-line-size mismatch from an error to a warning
- Use ALIGN and ALIGN_DOWN helpers instead of the alignment logic in
andes_dma_cache_inv() and andes_dma_cache_wback().
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
drivers/cache/andes_llcache.c | 56 ++++++++++++++++++-----------------
1 file changed, 29 insertions(+), 27 deletions(-)
diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index d5e382f3c801..d318b8009f7f 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -111,21 +111,17 @@ static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
unsigned long end = start + size;
- unsigned long line_size;
+ unsigned long line_size = andes_priv.andes_cache_line_size;
unsigned long flags;
- if (unlikely(start == end))
+ if (unlikely(!size))
return;
- line_size = andes_priv.andes_cache_line_size;
-
- start = start & (~(line_size - 1));
- end = ((end + line_size - 1) & (~(line_size - 1)));
+ start = ALIGN_DOWN(start, line_size);
+ end = ALIGN(end, line_size);
local_irq_save(flags);
-
andes_cpu_dcache_inval_range(start, end);
-
local_irq_restore(flags);
}
@@ -133,15 +129,15 @@ static void andes_dma_cache_wback(phys_addr_t paddr, size_t size)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
unsigned long end = start + size;
- unsigned long line_size;
+ unsigned long line_size = andes_priv.andes_cache_line_size;
unsigned long flags;
- if (unlikely(start == end))
+ if (unlikely(!size))
return;
- line_size = andes_priv.andes_cache_line_size;
- start = start & (~(line_size - 1));
- end = ((end + line_size - 1) & (~(line_size - 1)));
+ start = ALIGN_DOWN(start, line_size);
+ end = ALIGN(end, line_size);
+
local_irq_save(flags);
andes_cpu_dcache_wb_range(start, end);
local_irq_restore(flags);
@@ -159,14 +155,13 @@ static int andes_get_llc_line_size(struct device_node *np)
ret = of_property_read_u32(np, "cache-line-size", &andes_priv.andes_cache_line_size);
if (ret) {
- pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
+ pr_err("Cache: Failed to get cache-line-size\n");
return ret;
}
if (andes_priv.andes_cache_line_size != ANDES_CACHE_LINE_SIZE) {
- pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
- andes_priv.andes_cache_line_size);
- return -EINVAL;
+ pr_warn("Cache: Expected cache-line-size to be 64 bytes (found:%u)\n",
+ andes_priv.andes_cache_line_size);
}
return 0;
@@ -186,16 +181,18 @@ static const struct of_device_id andes_cache_ids[] = {
static int __init andes_cache_init(void)
{
struct resource res;
- int ret;
+ int ret = 0;
struct device_node *np __free(device_node) =
of_find_matching_node(NULL, andes_cache_ids);
- if (!of_device_is_available(np))
- return -ENODEV;
+ if (!of_device_is_available(np)) {
+ ret = -ENODEV;
+ goto err_ret;
+ }
ret = of_address_to_resource(np, 0, &res);
if (ret)
- return ret;
+ goto err_ret;
/*
* If IOCP is present on the Andes AX45MP core riscv_cbom_block_size
@@ -208,17 +205,22 @@ static int __init andes_cache_init(void)
return 0;
andes_priv.llc_base = ioremap(res.start, resource_size(&res));
- if (!andes_priv.llc_base)
- return -ENOMEM;
+ if (!andes_priv.llc_base) {
+ ret = -ENOMEM;
+ goto err_ret;
+ }
ret = andes_get_llc_line_size(np);
- if (ret) {
- iounmap(andes_priv.llc_base);
- return ret;
- }
+ if (ret)
+ goto err_unmap;
riscv_noncoherent_register_cache_ops(&andes_cmo_ops);
return 0;
+
+err_unmap:
+ iounmap(andes_priv.llc_base);
+err_ret:
+ return ret;
}
early_initcall(andes_cache_init);
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations
2026-03-30 10:27 ` [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations Hui Min Mina Chou
@ 2026-03-30 13:02 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-30 13:02 UTC (permalink / raw)
To: Hui Min Mina Chou, pjw, palmer, aou, alex, geert+renesas,
prabhakar.mahadev-lad.rj, magnus.damm, ben717, robh, krzk+dt,
conor+dt, jonathan.cameron, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc
Cc: tim609, alex749, az70021
On 30/03/2026 12:27, Hui Min Mina Chou wrote:
> This patch cleans up the Andes LLC cache driver:
> - improved error handling in andes_cache_init() by using goto labels
> - updated andes_dma_cache_inv/wback() to check for !size instead of
> start == end
> - cache-line-size mismatch from an error to a warning
> - Use ALIGN and ALIGN_DOWN helpers instead of the alignment logic in
> andes_dma_cache_inv() and andes_dma_cache_wback().
Please read submitting patches document. One thing per commit with
proper rationale WHY you are doing this.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/7] cache: andes_llcache: improve performance of LLC operation
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 1/7] cache: ax45mp_cache: refactor cache driver for generic Andes " Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations Hui Min Mina Chou
@ 2026-03-30 10:27 ` Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 4/7] cache: andes_llcache: centralize cache ops and use native WBINVAL Hui Min Mina Chou
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Hui Min Mina Chou @ 2026-03-30 10:27 UTC (permalink / raw)
To: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc
Cc: tim609, alex749, az70021, Hui Min Mina Chou, Leo Yu-Chi Liang
Eliminate get_cpu() on !CONFIG_SMP and switch readl/writel to their
relaxed variants to remove unnecessary fence instructions on I/O
memory access. The platform specification defines all I/O regions are
on channel 0 (point-to-point strongly ordered), so explicit fences are
not required [1][2][3]. Explicit memory barriers (mb) are added before
and after the CCTL loop to ensure overall memory consistency.
Also fix hart ID mapping by switching to cpuid_to_hartid_map() instead
of using the logical CPU ID directly. In AMP setups (e.g. Linux on
Hart 1, RTOS on Hart 0), Linux sees itself as CPU 0 but must access
Hart 1's CCTL registers, so using the logical ID would cause accidental
interference with other cores.
[1] platform spec 2.1.1: https://github.com/riscvarchive/riscv-platform-specs/blob/main/riscv-platform-spec.adoc?plain=1#L169
[2] privileged spec 3.6.5: https://github.com/riscv/riscv-isa-manual/blob/main/src/machine.adoc?plain=1#L2835
[3] riscv: asm/mmio.h: https://gitea.andestech.com/RD-SW/linux/src/branch/ast-v5_4_0-branch/arch/riscv/include/asm/mmio.h#L105
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
drivers/cache/andes_llcache.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index d318b8009f7f..57f666bc537a 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -66,7 +66,7 @@ static struct andes_priv andes_priv;
/* LLC operations */
static inline uint32_t andes_cpu_llc_get_cctl_status(void)
{
- return readl(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
+ return readl_relaxed(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
}
static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
@@ -74,16 +74,22 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
{
unsigned long line_size = andes_priv.andes_cache_line_size;
void __iomem *base = andes_priv.llc_base;
- int mhartid = smp_processor_id();
unsigned long pa;
+ int mhartid = 0;
+ if (IS_ENABLED(CONFIG_SMP))
+ mhartid = cpuid_to_hartid_map(get_cpu());
+ else
+ mhartid = cpuid_to_hartid_map(0);
+
+ mb(); /* complete earlier memory accesses before the cache flush */
while (end > start) {
csr_write(CSR_UCCTLBEGINADDR, start);
csr_write(CSR_UCCTLCOMMAND, l1_op);
pa = virt_to_phys((void *)start);
- writel(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
- writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
+ writel_relaxed(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
+ writel_relaxed(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
while ((andes_cpu_llc_get_cctl_status() &
ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
ANDES_LLC_CCTL_STATUS_IDLE)
@@ -91,6 +97,10 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
start += line_size;
}
+ mb(); /* issue later memory accesses after the cache flush */
+
+ if (IS_ENABLED(CONFIG_SMP))
+ put_cpu();
}
/* Write-back L1 and LLC entry */
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 4/7] cache: andes_llcache: centralize cache ops and use native WBINVAL
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
` (2 preceding siblings ...)
2026-03-30 10:27 ` [PATCH 3/7] cache: andes_llcache: improve performance of LLC operation Hui Min Mina Chou
@ 2026-03-30 10:27 ` Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache Hui Min Mina Chou
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Hui Min Mina Chou @ 2026-03-30 10:27 UTC (permalink / raw)
To: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc
Cc: tim609, alex749, az70021, Hui Min Mina Chou
Introduce andes_cpu_cache_operation() to centralize address
translation, alignment, and IRQ handling, removing the redundant
wrappers andes_cpu_dcache_wb_range and andes_cpu_dcache_inval_range.
This refactoring includes the following refinements:
- Consolidates address translation, boundary alignment, and IRQ handling
(local_irq_save/restore) into the central function.
- Make IRQ handling per cache line instead of across the entire cache
operation.
- Cleans up redundant intermediate wrapper functions
(andes_cpu_dcache_wb_range, andes_cpu_dcache_inval_range).
- wback_inv was chaining wback + inv separately; use the hardware's
native WBINVAL CCTL instead, which does both in one shot.
Signed-off-by: Alex Chun-Ju Lin <alex749@andestech.com>
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
drivers/cache/andes_llcache.c | 63 ++++++++++++-----------------------
1 file changed, 21 insertions(+), 42 deletions(-)
diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 57f666bc537a..0efa6e9c80bd 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -69,21 +69,29 @@ static inline uint32_t andes_cpu_llc_get_cctl_status(void)
return readl_relaxed(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
}
-static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
- unsigned int l1_op, unsigned int llc_op)
+static void andes_cpu_cache_operation(phys_addr_t paddr, size_t size,
+ unsigned int l1_op, unsigned int llc_op)
{
unsigned long line_size = andes_priv.andes_cache_line_size;
void __iomem *base = andes_priv.llc_base;
+ unsigned long start = (unsigned long)phys_to_virt(paddr);
+ unsigned long end = start + size;
+ unsigned long flags;
unsigned long pa;
int mhartid = 0;
+ start = ALIGN_DOWN(start, line_size);
+ end = ALIGN(end, line_size);
+
if (IS_ENABLED(CONFIG_SMP))
mhartid = cpuid_to_hartid_map(get_cpu());
else
mhartid = cpuid_to_hartid_map(0);
mb(); /* complete earlier memory accesses before the cache flush */
- while (end > start) {
+ for (; start < end; start += line_size) {
+ local_irq_save(flags);
+
csr_write(CSR_UCCTLBEGINADDR, start);
csr_write(CSR_UCCTLCOMMAND, l1_op);
@@ -95,7 +103,7 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
ANDES_LLC_CCTL_STATUS_IDLE)
;
- start += line_size;
+ local_irq_restore(flags);
}
mb(); /* issue later memory accesses after the cache flush */
@@ -103,60 +111,31 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
put_cpu();
}
-/* Write-back L1 and LLC entry */
-static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end)
-{
- andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_WB,
- ANDES_LLC_CCTL_PA_WB);
-}
-
-/* Invalidate the L1 and LLC entry */
-static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end)
-{
- andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_INVAL,
- ANDES_LLC_CCTL_PA_INVAL);
-}
-
static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
{
- unsigned long start = (unsigned long)phys_to_virt(paddr);
- unsigned long end = start + size;
- unsigned long line_size = andes_priv.andes_cache_line_size;
- unsigned long flags;
-
if (unlikely(!size))
return;
- start = ALIGN_DOWN(start, line_size);
- end = ALIGN(end, line_size);
-
- local_irq_save(flags);
- andes_cpu_dcache_inval_range(start, end);
- local_irq_restore(flags);
+ andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_INVAL,
+ ANDES_LLC_CCTL_PA_INVAL);
}
static void andes_dma_cache_wback(phys_addr_t paddr, size_t size)
{
- unsigned long start = (unsigned long)phys_to_virt(paddr);
- unsigned long end = start + size;
- unsigned long line_size = andes_priv.andes_cache_line_size;
- unsigned long flags;
-
if (unlikely(!size))
return;
- start = ALIGN_DOWN(start, line_size);
- end = ALIGN(end, line_size);
-
- local_irq_save(flags);
- andes_cpu_dcache_wb_range(start, end);
- local_irq_restore(flags);
+ andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_WB,
+ ANDES_LLC_CCTL_PA_WB);
}
static void andes_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
{
- andes_dma_cache_wback(paddr, size);
- andes_dma_cache_inv(paddr, size);
+ if (unlikely(!size))
+ return;
+
+ andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_WBINVAL,
+ ANDES_LLC_CCTL_PA_WBINVAL);
}
static int andes_get_llc_line_size(struct device_node *np)
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
` (3 preceding siblings ...)
2026-03-30 10:27 ` [PATCH 4/7] cache: andes_llcache: centralize cache ops and use native WBINVAL Hui Min Mina Chou
@ 2026-03-30 10:27 ` Hui Min Mina Chou
2026-03-30 12:51 ` Rob Herring (Arm)
2026-03-30 13:00 ` Krzysztof Kozlowski
2026-03-30 10:27 ` [PATCH 6/7] dts: riscv: update cache compatible strings to LLC Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 7/7] MAINTAINERS: Add maintainers for Andes cache driver Hui Min Mina Chou
6 siblings, 2 replies; 13+ messages in thread
From: Hui Min Mina Chou @ 2026-03-30 10:27 UTC (permalink / raw)
To: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc
Cc: tim609, alex749, az70021, Hui Min Mina Chou
The AX45MP-specific cache binding is renamed to a generic Last Level
Cache (LLC) schema, as the driver now supports more Andes CPU cores
beyond just AX45MP.
Updated compatible strings:
andestech,qilai-ax45mp-cache -> andestech,qilai-llcache
renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
andestech,ax45mp-cache -> andestech,llcache
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
...ache.yaml => andestech,andes-llcache.yaml} | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,andes-llcache.yaml} (76%)
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
similarity index 76%
rename from Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
rename to Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
index b135ffa4ab6b..5b97625edd37 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
@@ -2,17 +2,17 @@
# Copyright (C) 2023 Renesas Electronics Corp.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
+$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Andestech AX45MP L2 Cache Controller
+title: Andestech Last Level Cache Controller
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
- A level-2 cache (L2C) is used to improve the system performance by providing
- a large amount of cache line entries and reasonable access delays. The L2C
+ A last level cache (LLC) is used to improve the system performance by providing
+ a large amount of cache line entries and reasonable access delays. The LLC
is shared between cores, and a non-inclusive non-exclusive policy is used.
select:
@@ -20,7 +20,7 @@ select:
compatible:
contains:
enum:
- - andestech,ax45mp-cache
+ - andestech,llcache
required:
- compatible
@@ -29,9 +29,9 @@ properties:
compatible:
items:
- enum:
- - andestech,qilai-ax45mp-cache
- - renesas,r9a07g043f-ax45mp-cache
- - const: andestech,ax45mp-cache
+ - andestech,qilai-llcache
+ - renesas,r9a07g043f-llcache
+ - const: andestech,llcache
- const: cache
reg:
@@ -73,7 +73,7 @@ allOf:
properties:
compatible:
contains:
- const: andestech,qilai-ax45mp-cache
+ const: andestech,qilai-llcache
then:
properties:
@@ -91,7 +91,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
cache-controller@13400000 {
- compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
+ compatible = "renesas,r9a07g043f-llcache", "andestech,llcache",
"cache";
reg = <0x13400000 0x100000>;
interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache
2026-03-30 10:27 ` [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache Hui Min Mina Chou
@ 2026-03-30 12:51 ` Rob Herring (Arm)
2026-03-30 13:00 ` Krzysztof Kozlowski
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring (Arm) @ 2026-03-30 12:51 UTC (permalink / raw)
To: Hui Min Mina Chou
Cc: krzk+dt, jonathan.cameron, pjw, palmer, conor+dt, aou, alex749,
az70021, linux-renesas-soc, linux-kernel,
prabhakar.mahadev-lad.rj, devicetree, linux-riscv, geert+renesas,
alex, magnus.damm, ben717, tim609
On Mon, 30 Mar 2026 18:27:22 +0800, Hui Min Mina Chou wrote:
> The AX45MP-specific cache binding is renamed to a generic Last Level
> Cache (LLC) schema, as the driver now supports more Andes CPU cores
> beyond just AX45MP.
>
> Updated compatible strings:
> andestech,qilai-ax45mp-cache -> andestech,qilai-llcache
> renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
> andestech,ax45mp-cache -> andestech,llcache
>
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> ---
> ...ache.yaml => andestech,andes-llcache.yaml} | 20 +++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
> rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,andes-llcache.yaml} (76%)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml: $id: Cannot determine base path from $id, relative path/filename doesn't match actual path or filename
$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml
file: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260330102724.1012470-6-minachou@andestech.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache
2026-03-30 10:27 ` [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache Hui Min Mina Chou
2026-03-30 12:51 ` Rob Herring (Arm)
@ 2026-03-30 13:00 ` Krzysztof Kozlowski
1 sibling, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-30 13:00 UTC (permalink / raw)
To: Hui Min Mina Chou, pjw, palmer, aou, alex, geert+renesas,
prabhakar.mahadev-lad.rj, magnus.damm, ben717, robh, krzk+dt,
conor+dt, jonathan.cameron, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc
Cc: tim609, alex749, az70021
On 30/03/2026 12:27, Hui Min Mina Chou wrote:
> The AX45MP-specific cache binding is renamed to a generic Last Level
> Cache (LLC) schema, as the driver now supports more Andes CPU cores
> beyond just AX45MP.
>
> Updated compatible strings:
> andestech,qilai-ax45mp-cache -> andestech,qilai-llcache
> renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
> andestech,ax45mp-cache -> andestech,llcache
Why? No explanations and that is clear ABI break.
=
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] dts: riscv: update cache compatible strings to LLC
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
` (4 preceding siblings ...)
2026-03-30 10:27 ` [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache Hui Min Mina Chou
@ 2026-03-30 10:27 ` Hui Min Mina Chou
2026-03-30 13:03 ` Krzysztof Kozlowski
2026-03-30 10:27 ` [PATCH 7/7] MAINTAINERS: Add maintainers for Andes cache driver Hui Min Mina Chou
6 siblings, 1 reply; 13+ messages in thread
From: Hui Min Mina Chou @ 2026-03-30 10:27 UTC (permalink / raw)
To: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc
Cc: tim609, alex749, az70021, Hui Min Mina Chou
Update the cache driver compatible strings from ax45mp-cache to llcache
for both Qilai and RZ/Five platforms.
This follows the Andes cache driver refactoring to use more generic
Last Level Cache (LLC) naming.
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
arch/riscv/boot/dts/andes/qilai.dtsi | 4 ++--
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
index de3de32f8c39..a7436cbf6f69 100644
--- a/arch/riscv/boot/dts/andes/qilai.dtsi
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -137,8 +137,8 @@ plmt: timer@100000 {
};
l2_cache: cache-controller@200000 {
- compatible = "andestech,qilai-ax45mp-cache",
- "andestech,ax45mp-cache", "cache";
+ compatible = "andestech,qilai-llcache",
+ "andestech,llcache", "cache";
reg = <0x0 0x00200000 0x0 0x100000>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
cache-line-size = <64>;
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 571de3cafa82..83a5d4d41f8e 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -144,7 +144,7 @@ plic: interrupt-controller@12c00000 {
};
l2cache: cache-controller@13400000 {
- compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
+ compatible = "renesas,r9a07g043f-llcache", "andestech,llcache",
"cache";
reg = <0x0 0x13400000 0x0 0x100000>;
interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 6/7] dts: riscv: update cache compatible strings to LLC
2026-03-30 10:27 ` [PATCH 6/7] dts: riscv: update cache compatible strings to LLC Hui Min Mina Chou
@ 2026-03-30 13:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-30 13:03 UTC (permalink / raw)
To: Hui Min Mina Chou, pjw, palmer, aou, alex, geert+renesas,
prabhakar.mahadev-lad.rj, magnus.damm, ben717, robh, krzk+dt,
conor+dt, jonathan.cameron, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc
Cc: tim609, alex749, az70021
On 30/03/2026 12:27, Hui Min Mina Chou wrote:
> Update the cache driver compatible strings from ax45mp-cache to llcache
Driver? DTS is for hardware.
> for both Qilai and RZ/Five platforms.
> This follows the Andes cache driver refactoring to use more generic
Nope, driver changes cannot be the reason to change DTS.
> Last Level Cache (LLC) naming.
>
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> ---
> arch/riscv/boot/dts/andes/qilai.dtsi | 4 ++--
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
> index de3de32f8c39..a7436cbf6f69 100644
> --- a/arch/riscv/boot/dts/andes/qilai.dtsi
> +++ b/arch/riscv/boot/dts/andes/qilai.dtsi
> @@ -137,8 +137,8 @@ plmt: timer@100000 {
> };
>
> l2_cache: cache-controller@200000 {
> - compatible = "andestech,qilai-ax45mp-cache",
> - "andestech,ax45mp-cache", "cache";
> + compatible = "andestech,qilai-llcache",
> + "andestech,llcache", "cache";
NAK, actual impact on users.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 7/7] MAINTAINERS: Add maintainers for Andes cache driver
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
` (5 preceding siblings ...)
2026-03-30 10:27 ` [PATCH 6/7] dts: riscv: update cache compatible strings to LLC Hui Min Mina Chou
@ 2026-03-30 10:27 ` Hui Min Mina Chou
6 siblings, 0 replies; 13+ messages in thread
From: Hui Min Mina Chou @ 2026-03-30 10:27 UTC (permalink / raw)
To: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc
Cc: tim609, alex749, az70021, Hui Min Mina Chou
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 832 bytes --]
Here add maintainer information for Andes cache driver.
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 23d88c825175..e95efbcd6d39 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1863,6 +1863,14 @@ S: Supported
F: Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
F: drivers/spi/spi-atcspi200.c
+ANDES CACHE DRIVER
+M: Alex Chun-Ju Lin <alex749@andestech.com>
+M: Leo Yu-Chi Liang <ycliang@andestech.com>
+M: Mina Hui Min Chou <minachou@andestech.com>
+S: Supported
+F: Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
+F: drivers/cache/andes_llcache.c
+
ANDROID DRIVERS
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: Arve Hjønnevåg <arve@android.com>
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread