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Fri, 09 Feb 2024 05:56:59 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWqzdyXPQpxuboeQxrzdVEqFAjU+CVslIikEPsUW2QQfQZXYGuwwroNabViw65p+INrxFkbWKR4aLNysYn8znZWXwpiPcZJhXQaN7r82SfEfo0susUG3IoLcRzoDavxVp48t9pbrchLcyp33CQYXUs72wdhHr6E919JKxuFxf1Y5GK+pwuXg5WbNj+IM1MrLEd2nVo0n7pCdhrO+SqUMyx6AzjDFNQM/b7uW3hYlqPMkzTB075tJxSxm77z3ZY3iYGOV1dcWPqynNKaNnhNOdfL4YFhPpAJ108SgjTkKFagnCnQ1w8PWv4Pnwp1v3EcFDUKZBFN1hZmVQKRM9DgUagyNtMW7qrW+ygkR+Fa0gTeLqBL5ojuKKu7GtZm9jqg9DwD1amfLWFicbQMRLh1kcjQwzxWoadTmlA68oxQ18XQJZZ2p1tdOCKfzXZ+uZy+sP4EKQ83pcq/DGViab3cFG4/5t/C5Nk/WlxfIZIa1y9+PuqYrCc9nOd61vfneEXo/GgCL7V0TFxFHwmeZIX3pvUt3gek9gg26DCKiG0qiNIx6+CkFP4q5OyWQbppcum6/EBm7VKwrlOu5ojo2Jx6AwyQ1aqHZNHycjcKaGD4Fvww7jINzjl5/nc= Received: from [192.168.2.107] ([79.115.63.202]) by smtp.gmail.com with ESMTPSA id m6-20020a05600c3b0600b0040e9d507424sm789392wms.5.2024.02.09.05.56.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 05:56:58 -0800 (PST) Message-ID: Date: Fri, 9 Feb 2024 13:56:56 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property Content-Language: en-US To: Conor Dooley , Geert Uytterhoeven Cc: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> <20240208135045.3728927-2-tudor.ambarus@linaro.org> <20240208-grating-legwarmer-0a04cfb04d61@spud> From: Tudor Ambarus In-Reply-To: <20240208-grating-legwarmer-0a04cfb04d61@spud> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit + Geert On 2/8/24 18:24, Conor Dooley wrote: > On Thu, Feb 08, 2024 at 01:50:34PM +0000, Tudor Ambarus wrote: >> There are instances of the same IP that are configured by the integrator >> with different FIFO depths. Introduce the fifo-depth property to allow >> such nodes to specify their FIFO depth. >> >> We haven't seen SPI IPs with different FIFO depths for RX and TX, thus >> introduce a single property. > > Some citation attached to this would be nice. "We haven't seen" offers > no detail as to what IPs that allow this sort of configuration of FIFO > size that you have actually checked. > > I went and checked our IP that we use in FPGA fabric, which has a > configurable fifo depth. It only has a single knob for both RX and TX > FIFOs. The Xilinx xps spi core also has configurable FIFOs, but again RX > and TX sizes are tied there. At least that's a sample size of three. > > One of our guys is working on support for the IP I just mentioned and > would be defining a vendor property for this, so > Reviewed-by: Conor Dooley > Thanks, Conor. I had in mind that SPI has a shift register and it's improbable to have different FIFO depths for RX and TX. At least I don't see how it would work, I guess it will use the minimum depth between the two? I grepped by "fifo" in the spi bindings and I now see that renesas is using dedicated properties for RX and TX, but I think that there too the FIFOs have the same depths. Looking into drivers/spi/spi-sh-msiof.c I see that the of_device_id.data contains 64 bytes FIFOs for RX and TX, regardless of the compatible. Geert, any idea if the FIFO depths can differ for RX and TX in spi-sh-msiof.c? Anyway, even if there are such imbalanced architectures, I guess we can consider them when/if they appear? (add rx/tx-fifo-depth dt properties) Cheers, ta ---- $ git grep fifo Documentation/devicetree/bindings/spi/ Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml: atmel,fifo-size: Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml: atmel,fifo-size = <32>; Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: cdns,fifo-depth: Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: cdns,fifo-depth: Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: cdns,fifo-depth: Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: cdns,fifo-width: Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: - cdns,fifo-depth Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: - cdns,fifo-width Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: cdns,fifo-depth = <128>; Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: cdns,fifo-width = <4>; Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml: renesas,tx-fifo-size: Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml: Override the default TX fifo size. Unit is words. Ignored if 0. Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml: renesas,rx-fifo-size: Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml: Override the default RX fifo size. Unit is words. Ignored if 0. Documentation/devicetree/bindings/spi/spi-sifive.yaml: sifive,fifo-depth: Documentation/devicetree/bindings/spi/spi-sifive.yaml: sifive,fifo-depth = <8>;