Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 23/01/2025 12:42, Dmitry Baryshkov wrote:
> On Thu, Jan 23, 2025 at 12:34:28PM +0100, Krzysztof Kozlowski wrote:
>> On 13/01/2025 13:13, Dmitry Baryshkov wrote:
>>> On Mon, Jan 13, 2025 at 12:02:54PM +0100, Krzysztof Kozlowski wrote:
>>>> On 13/01/2025 09:29, Dmitry Baryshkov wrote:
>>>>> On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
>>>>>> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
>>>>>>> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
>>>>>>>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
>>>>>>>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
>>>>>>>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
>>>>>>>>>> differences worth noting:
>>>>>>>>>>
>>>>>>>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>>>>>>>>>>    offsets were just switched.  Currently these registers are not used
>>>>>>>>>>    in the driver, so the easiest is to document both but keep them
>>>>>>>>>>    commented out to avoid conflict.
>>>>>>>>>>
>>>>>>>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>>>>>>>>>    parents before they are prepared and initial rate is set.  Therefore
>>>>>>>>>>    assigned-clock-parents are not working here and driver is responsible
>>>>>>>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
>>>>>>>>>
>>>>>>>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
>>>>>>>>
>>>>>>>> No - must be gated accross reparent - so opposite.
>>>>>>>>
>>>>>>>>> CLK_OPS_PARENT_ENABLE ?
>>>>>>>>
>>>>>>>> Yes, but does not work. Probably enabling parent, before
>>>>>>>> assigned-clocks-parents, happens still too early:
>>>>>>>>
>>>>>>>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
>>>>>>>> [    1.623556] PLL(0) lock failed
>>>>>>>> [    1.624650] ------------[ cut here ]------------
>>>>>>>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
>>>>>>>> configuration.
>>>>>>>>
>>>>>>>> Or maybe something is missing in the DSI PHY PLL driver?
>>>>>>>
>>>>>>> Do you have the no-zero-freq workaround?
>>>>>>
>>>>>> Yes, it is necessary also for my variant. I did not include it here, but
>>>>>> I should mention it in the cover letter.
>>>>>
>>>>> Could you please possibly backtrace the corresponding enable() calls?
>>>>
>>>>
>>>> It's the same backtrace I shared some time ago in internal discussions:
>>>> https://pastebin.com/kxUFgzD9
>>>> Unless you ask for some other backtrace?
>>>>
>>>>> I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
>>>>> such requirement should be handled by the framework instead of having
>>>>> the drivers to manually reparent the clocks.
>>>>
>>>> I don't know how exactly you would like to solve it. The clocks can be
>>>> reparented only after some other device specific enable sequence. It's
>>>> the third device here, but not reflected in the clocks hierarchy. Maybe
>>>> it's the result how entire Display device nodes were designed in the
>>>> first place?
>>>>
>>>> Assigned clocks are between DSI PHY and DISP cc, but they are a property
>>>> of DSI controller. This looks exactly too specific for core to handle
>>>> and drivers, not framework, should manually reparent such clocks.
>>>> Otherwise we need
>>>> "clk_pre_prepare_callback_if_we_are_called_when_phy_is_disabled" sort of
>>>> callback.
>>>
>>> What kind of PHY programming is required? Is enabling the PLL enough or
>>> does it need anything else? Are the PLL supplies properly enabled at
>>> this point?
>>>
>>
>> I don't know exactly and checking is tricky. I tried to use
>> CLK_OPS_PARENT_ENABLE - with equivalent code, setting proper parents but
>> without enabling the DSI PHY PLL manually just with
>> CLK_OPS_PARENT_ENABLE - but then you have multiple:
>>
>> dsi0_pll_bit_clk: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> 
> This really looks as if a part of the DSI PHY is unpowered. If you are
> sure about your DSI and DSI PHY supplies (and power domains) then I also
> have no other ideas.

Yes, I triple checked them with downstream and with schematics.

The rate setting - which is being discussed/fixed here - is in:
msm_dsi_host_power_on()
which does:

    regulator_bulk_enable()
    pm_runtime_get_sync(&msm_host->pdev->dev);
    ret = cfg_hnd->ops->link_clk_set_rate(msm_host);


If I refactor this code into:

    regulator_bulk_enable()
    pm_runtime_get_sync(&msm_host->pdev->dev);
    MY_NEW_PREPARE_REPARENT_UNPREPARE()
    ret = cfg_hnd->ops->link_clk_set_rate(msm_host);

and use CLK_OPS_PARENT_ENABLE, I still got mentioned errors with calltrace:

dev_pm_opp_set_rate (drivers/opp/core.c:1357)
    ^^^^^^^^ line numbers won't help you, so explaining:
             this is exactly in dsi_link_clk_set_rate_6g
dsi_link_clk_set_rate_6g (drivers/gpu/drm/msm/dsi/dsi_host.c:391)
msm_dsi_host_power_on (drivers/gpu/drm/msm/dsi/dsi_host.c:2520)

This is actually weird, because PHY is powered in this case. I would
consider CLK_OPS_PARENT_ENABLE() to be equal to my clk_prepare_enable
from this patch, but somehow it is not equivalent.

> 
> Abhinav? Any input from your side? Or from Taniya Das?
> 
>>
Best regards,
Krzysztof