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Wed, 25 Mar 2026 03:19:17 -0700 (PDT) Message-ID: Date: Wed, 25 Mar 2026 12:19:15 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] PCI: rzg3s-host: Prepare System Controller handling for multiple PCIe channels To: Prabhakar , Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260318124450.163471-5-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: <20260318124450.163471-5-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, Prabhakar, On 3/18/26 14:44, Prabhakar wrote: > From: Lad Prabhakar > > Prepare the driver to handle multiple PCIe channels with distinct System > Controller register sets, as required by RZ/V2H(P). The current design > stores a single sysc_info structure per SoC, which is insufficient for > multi-channel configurations. > > Introduce channel identifiers and extend struct rzg3s_pcie_soc_data to > hold a sysc_info array indexed per PCIe channel. Add a channel field to > struct rzg3s_pcie_host and select the appropriate System Controller > information during probe based on the channel. > > Keep existing single-channel SoCs functionally unchanged while > preparing the driver for RZ/V2H(P) multi-channel support. > > Signed-off-by: Lad Prabhakar > --- > drivers/pci/controller/pcie-rzg3s-host.c | 48 ++++++++++++++++-------- > 1 file changed, 33 insertions(+), 15 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c > index c61e011f8302..a629e861bbd0 100644 > --- a/drivers/pci/controller/pcie-rzg3s-host.c > +++ b/drivers/pci/controller/pcie-rzg3s-host.c > @@ -241,6 +241,18 @@ struct rzg3s_pcie_msi { > int irq; > }; > > +/** > + * enum rzg3s_pcie_channel_id - RZ/G3S PCIe channel IDs > + * @RZG3S_PCIE_CHANNEL_ID_0: PCIe channel 0 > + * @RZG3S_PCIE_CHANNEL_ID_1: PCIe channel 1 > + * @RZG3S_PCIE_CHANNEL_ID_MAX: Max PCIe channels > + */ > +enum rzg3s_pcie_channel_id { > + RZG3S_PCIE_CHANNEL_ID_0, > + RZG3S_PCIE_CHANNEL_ID_1, Just saying... based on Bjorn feedback on patch 3/5 the names used here would have to be adjusted accordingly. Maybe controller_id? Same for the other patches. Thank you, Claudiu