Re: [PATCH 3/3] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 17/01/2024 11:25, Siddharth Vadapalli wrote:
> TI's J722S SoC has one instance of a Gen3 Single Lane PCIe controller.
> The controller on J722S SoC is similar to the one present on TI's AM64
> SoC, with the difference being that the controller on AM64 SoC supports
> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
> 
> Update the bindings with a new compatible for J722S SoC and enforce checks
> for "num-lanes" and "max-link-speed".
> 
> Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>  .../devicetree/bindings/pci/ti,j721e-pci-host.yaml  | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> index 005546dc8bd4..b7648f7e73c9 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> @@ -14,6 +14,7 @@ properties:
>    compatible:
>      oneOf:
>        - const: ti,j721e-pcie-host
> +      - const: ti,j722s-pcie-host
>        - const: ti,j784s4-pcie-host
>        - description: PCIe controller in AM64
>          items:
> @@ -134,6 +135,18 @@ allOf:
>            minimum: 1
>            maximum: 4
>  
> +  - if:
> +      properties:
> +        compatible:
> +          items:

enum

> +            - const: ti,j722s-pcie-host
> +    then:
> +      properties:
> +        max-link-speed:
> +          const: 3
> +        num-lanes:
> +          const: 1

Similarly to previous patch: What is the point of all this? You have
direct mapping compatible-property, so encode these in the drivers.

Best regards,
Krzysztof