From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Tinghan Shen <tinghan.shen@mediatek.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Jianjun Wang <jianjun.wang@mediatek.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v1 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes
Date: Wed, 19 Oct 2022 10:55:49 +0200 [thread overview]
Message-ID: <c30fbc60-bcdf-71f5-0db7-bd9bb27ddd37@collabora.com> (raw)
In-Reply-To: <20221017070858.13902-3-tinghan.shen@mediatek.com>
Il 17/10/22 09:08, Tinghan Shen ha scritto:
> Add pcie and pcie phy nodes for mt8195.
>
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 143 +++++++++++++++++++++++
> 1 file changed, 143 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index d03f0c2b8233..903e92d6156f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1182,6 +1182,104 @@
> status = "disabled";
> };
>
> + pcie0: pcie@112f0000 {
> + compatible = "mediatek,mt8195-pcie",
> + "mediatek,mt8192-pcie";
..snip..
> +
> + phys = <&pciephy>;
> + phy-names = "pcie-phy";
> +
> + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
You're missing the resets:
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
reset-names = "mac";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
..snip..
> + };
> +
> + pcie1: pcie@112f8000 {
> + compatible = "mediatek,mt8195-pcie",
> + "mediatek,mt8192-pcie";
..snip..
> + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
Here too:
resets = <&infracfg_ao MT8195_INFRA_RST2_USBSIF_P1_SWRST>,
<&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
reset-names = "phy", "mac";
> +
> + #interrupt-cells = <1>;
..snip..
> @@ -1241,6 +1339,34 @@
> reg = <0x189 0x2>;
> bits = <7 5>;
> };
> + pciephy_rx_ln1: pciephy-rx-ln1@190 {
> + reg = <0x190 0x1>;
> + bits = <0 4>;
> + };
> + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 {
Please run dtbs_check and try to build the kernel before pushing commits upstream.
This will give you a not-so-nice warning and that shall not happen.
You can solve it by naming these nodes like:
pciephy-rx-ln1@190,1
pciephy-tx-ln1-nmos@190,2
...etc
Regards,
Angelo
next prev parent reply other threads:[~2022-10-19 9:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-17 7:08 [PATCH v1 0/3] Add driver nodes for MT8195 SoC Tinghan Shen
2022-10-17 7:08 ` [PATCH v1 1/3] dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support Tinghan Shen
2022-10-17 18:42 ` Rob Herring
2022-10-18 1:49 ` TingHan Shen (沈廷翰)
2022-10-17 7:08 ` [PATCH v1 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes Tinghan Shen
2022-10-19 8:55 ` AngeloGioacchino Del Regno [this message]
2022-10-20 2:10 ` Jianjun Wang
2022-10-17 7:08 ` [PATCH v1 3/3] arm64: dts: mt8195: Add venc node Tinghan Shen
2022-10-18 22:41 ` Krzysztof Kozlowski
2022-10-19 8:51 ` AngeloGioacchino Del Regno
2022-10-19 8:56 ` Irui Wang
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