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Sat, 11 Apr 2026 09:47:28 -0500 Received: from [172.24.233.103] (uda0132425.dhcp.ti.com [172.24.233.103]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 63BElNk41983236; Sat, 11 Apr 2026 09:47:24 -0500 Message-ID: Date: Sat, 11 Apr 2026 20:17:22 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/7] arm64: dts: ti: k3-am62a7-sk: Split r5f memory region To: Markus Schneider-Pargmann , Bjorn Andersson , Mathieu Poirier , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Suman Anna , Nishanth Menon , Tero Kristo CC: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , "Kendall Willis" , Akashdeep Kaur , , , , References: <20260318-topic-am62a-ioddr-dt-v6-19-v3-0-c41473cb23c3@baylibre.com> <20260318-topic-am62a-ioddr-dt-v6-19-v3-4-c41473cb23c3@baylibre.com> <8673745d-aad2-49d3-b3af-556de7037b69@ti.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TNXJjl19mROgg4yd+fgxY/4cGIbWm1xh+jABt4ocNuD86Q9GXOUW95WFkIyTM5Ys+w9xgGUeNYx6GRv0ui/TD83TtL2YHuCqH1W8CeUkVoE+2Ud8nSf6I4qCgYqBBBzeLVcLfo7yQ1QoxXunrIHjn7KSL5mB34+YYxdmrwr5pJLDrMBOmK3ovWKWprla6DODbxI84xFXY9fHs6PcAbCxvDRqXcwniKZ09FahKPoFErBz2jUoq9pAeHk/H8R4yGsZ+e8qWTeBJM7taZwDunnbVUHv9VDY7SofzNsqo9QSrjeAfyARle052OUoXz2aG1BnKJhoPDzSgUNAM+A7dlY8xwJu/2vmYlKQJt4lFIYmDSDnG+4dGHdyFzaVcuDR/TQn0IJPaaN62SNXBGsbOgc2Dj8EMtyy+EiWMvOX8k1wq1zY5uz4JkfKCwrrcFg+BHkq X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2026 14:47:29.3336 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 558823d5-0f14-4159-5d1a-08de97d94168 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR10MB4357 On 10/04/26 19:12, Markus Schneider-Pargmann wrote: > Hi Vignesh, > > On Fri Apr 10, 2026 at 6:30 AM CEST, Vignesh Raghavendra wrote: >> Hi Markus >> >> On 18/03/26 20:43, Markus Schneider-Pargmann (TI) wrote: >>> Split the firmware memory region in more specific parts so it is better >>> described where to find which information. Specifically the LPM metadata >>> region is important as bootloader software like U-Boot has to know where >>> that data is to be able to read that data. >>> >>> Signed-off-by: Markus Schneider-Pargmann (TI) >>> --- >>> arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 40 +++++++++++++++++++++++++++++++-- >>> 1 file changed, 38 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts >>> index e99bdbc2e0cbdf858f1631096f9c2a086191bab3..c381cc33064ec427751a9ac5bcdff745a9559a89 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts >>> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts >>> @@ -59,9 +59,33 @@ wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { >>> no-map; >>> }; >>> >>> - wkup_r5fss0_core0_memory_region: memory@9c900000 { >>> + wkup_r5fss0_core0_ipc_region: memory@9c900000 { >> >> There are still references to wkup_r5fss0_core0_memory_region in >> k3-am62a-ti-ipc-firmware.dtsi (same comment applies to next 2 patches as >> well) >> >> Dont those need to be updated too? > > I only updated the sk boards as these are the only ones that have IO+DDR > support that I know works and need the new memory region layout. But > thinking about this, updating the memory region structure shouldn't be a > problem for the other boards either, of course I can't tell if IO+DDR > would work on them, but the new memory region layout shouldn't break > anything. I am not talking about updating other boards, but specifically about k3-am62*-ti-ipc-firmware.dtsi which have a phandle reference to wkup_r5fss0_core0_memory_region. Therefore any dts trying to include this dtsi would fail to compile post this series. Please if these dtsi files > > I can respin the series or do a followup series with modifications for > all boards if you like. > > Best > Markus -- Regards Vignesh https://ti.com/opensource