From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C4816EB6D; Fri, 21 Jun 2024 10:02:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718964159; cv=none; b=CGnYtg9cL0AGualWdo/5Ue+yyBCKTPA3iqf8JjzQDkrKUROmmxjjKtceEpzuqA1juFfz4stp1nUYqWhwYKVV3aZyfkXuvehXIvKHpyWvXv9qJDfojwV8yKwzT04S2ejwgsHnmjtE+m5yB3SKnV2d8aY++mr0xYUayNjuhkWm8XM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718964159; c=relaxed/simple; bh=dmwsNvDKdvJyzog0BmeRIafnVzdlhm+iSDk33lXZPfo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=c56/YRT8bmpNcgN8shlKaK9bPo78ML2cd/WU8AshW67x7MBaqpvYaO/772+IQvg4RGBZwNWe73z+nE9bB9AxIbeJRFrA9k5MWrOkkLY8BbJ+mQw3io3lGNQTkbTvefqnAw1EMmi0hQYqQz7P7FY49yN+4xAVRJbnP1D6dsaHdt0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F/xsUEMs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F/xsUEMs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 491BBC2BBFC; Fri, 21 Jun 2024 10:02:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718964158; bh=dmwsNvDKdvJyzog0BmeRIafnVzdlhm+iSDk33lXZPfo=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=F/xsUEMsS04zCX8+SaxYsPUhm75Yu/RgnmwFnjWNa2r8esrMvPBl/oI1k0AYPKxja 5iHxbHR08oU4yLXxEQBTLo3Ofr8QOQsyNsKJyXo0PC1FpOPg5uaeN+km9UzwuFdzq+ WhzIkK47LNLg3I9zaXIUA3WxEMmdC3PhKRp+TCJwmfD9ctcCtmJGjt8/tC9XUvanyq iv4eYdtgW54d3c0PACWzKPFQ1n85eOOVoa1y2blkrIxnA1BbyYoXBvNFpWZ+foIEzl agenxxmoYDkecirxZ0Neghibe+ng3PpU2q8b5/4mqFRzJThvI+JkZ5IVDQ35yOjmt6 +YHV7iOVrDCBg== Message-ID: Date: Fri, 21 Jun 2024 12:02:31 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] media: dt-bindings: media: camss: Add qcom,sc7180-camss binding To: gchan9527@gmail.com, Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> <20240621-b4-sc7180-camss-v1-1-14937929f30e@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 21/06/2024 11:40, George Chan via B4 Relay wrote: > From: George Chan > > Add bindings for qcom,sc7180-camss in order to support the camera > subsystem for sm7125 as found in the Xiaomi Redmi 9 Pro cellphone. > > Signed-off-by: George Chan Subject: just one media (first). No need to write media: media: ... A nit, subject: drop second/last, redundant "binding". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > --- > .../bindings/media/qcom,sc7180-camss.yaml | 324 +++++++++++++++++++++ > 1 file changed, 324 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml > new file mode 100644 > index 000000000000..4dc10c32ee9c > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml > @@ -0,0 +1,324 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sc7180-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm CAMSS ISP What is CAMSS? > + > +maintainers: > + - Robert Foss For sure this is not true. Robert does not work in Linaro and I doubt he cares that much about camss. > + > +description: | Do not need '|' unless you need to preserve formatting. > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms > + > +properties: > + compatible: > + const: qcom,sc7180-camss > + > + clocks: > + minItems: 25 Drop minItems > + maxItems: 25 > + > + clock-names: > + items: > + - const: camnoc_axi > + - const: cpas_ahb > + - const: cphy_rx_src > + - const: csi0 > + - const: csi1 > + - const: csi2 > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy3 > + - const: csiphy3_timer > + - const: gcc_camera_ahb > + - const: gcc_camera_axi > + - const: soc_ahb > + - const: vfe0_axi > + - const: vfe0 > + - const: vfe0_cphy_rx > + - const: vfe1_axi > + - const: vfe1 > + - const: vfe1_cphy_rx > + - const: vfe_lite > + - const: vfe_lite_cphy_rx > + > + interrupts: > + minItems: 10 Drop minItems > + maxItems: 10 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: vfe0 > + - const: vfe1 > + - const: vfe_lite > + > + iommus: > + maxItems: 4 > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@2: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@3: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + reg: > + minItems: 10 Drop minItems > + maxItems: 10 > + > + reg-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: vfe0 > + - const: vfe1 > + - const: vfe_lite > + > + vdda-phy-supply: > + description: > + Phandle to a regulator supply to PHY core block. > + > + vdda-pll-supply: > + description: > + Phandle to 1.8V regulator supply to PHY refclk pll block. > + > +required: > + - clock-names > + - clocks > + - compatible Keep the list ordered, the same as list properties. > + - interrupt-names > + - interrupts > + - iommus > + - power-domains > + - reg > + - reg-names > + - vdda-phy-supply > + - vdda-pll-supply > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: camss@acb3000 { > + compatible = "qcom,sc7180-camss"; > + > + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, Missed alignment with previous <. > + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, > + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, > + <&clock_camcc CAM_CC_CSIPHY0_CLK>, > + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&clock_camcc CAM_CC_CSIPHY1_CLK>, > + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&clock_camcc CAM_CC_CSIPHY2_CLK>, > + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&clock_camcc CAM_CC_CSIPHY3_CLK>, > + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&clock_camcc CAM_CC_SOC_AHB_CLK>, > + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, > + <&clock_camcc CAM_CC_IFE_0_CLK>, > + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, > + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, > + <&clock_camcc CAM_CC_IFE_1_CLK>, > + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; > + > + clock-names = "camnoc_axi", > + "cpas_ahb", Same problem. > + "csi0", > + "csi1", > + "csi2", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy3", > + "csiphy3_timer", > + "gcc_camera_ahb", > + "gcc_camera_axi", > + "soc_ahb", > + "vfe0_axi", > + "vfe0", > + "vfe0_cphy_rx", > + "vfe1_axi", > + "vfe1", > + "vfe1_cphy_rx", > + "vfe_lite", > + "vfe_lite_cphy_rx"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "vfe0", > + "vfe1", > + "vfe_lite"; > + > + iommus = <&apps_smmu 0x820 0x0>, > + <&apps_smmu 0x840 0x0>, > + <&apps_smmu 0x860 0x0>; > + > + power-domains = <&camcc IFE_0_GDSC>, > + <&camcc IFE_1_GDSC>, > + <&camcc TITAN_TOP_GDSC>; > + > + reg = <0 0xacb3000 0 0x1000>, reg is always the second property. See DTS coding style. > + <0 0xacba000 0 0x1000>, > + <0 0xacc8000 0 0x1000>, > + <0 0xac65000 0 0x1000>, > + <0 0xac66000 0 0x1000>, > + <0 0xac67000 0 0x1000>, > + <0 0xac68000 0 0x1000>, > + <0 0xacaf000 0 0x4000>, > + <0 0xacb6000 0 0x4000>, > + <0 0xacc4000 0 0x4000>; > + > + reg-names = "csid0", So this will be the third property. Best regards, Krzysztof