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Fri, 22 Aug 2025 11:32:49 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 22 Aug 2025 11:32:49 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 22 Aug 2025 11:32:49 -0500 Received: from [10.249.139.51] ([10.249.139.51]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57MGWd6e3822193; Fri, 22 Aug 2025 11:32:40 -0500 Message-ID: Date: Fri, 22 Aug 2025 22:02:37 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/33] arm64: dts: ti: k3-j7200: Enable remote processors at board level To: "Kumar, Udit" , , , , , , CC: , , , , , References: <20250814223839.3256046-1-b-padhi@ti.com> <20250814223839.3256046-2-b-padhi@ti.com> Content-Language: en-US From: Beleswar Prasad Padhi In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Hi Udit, On 8/15/2025 8:00 AM, Kumar, Udit wrote: > Hello Beleswar, > > On 8/15/2025 4:08 AM, Beleswar Padhi wrote: >> Remote Processors defined in top-level J7200 SoC dtsi files are >> incomplete without the memory carveouts and mailbox assignments which >> are only known at board integration level. >> >> Therefore, disable the remote processors at SoC level and enable them at >> board level where above information is available. >> >> Signed-off-by: Beleswar Padhi >> --- >>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi       | 3 +++ >>   arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 3 +++ >>   arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi     | 9 +++++++++ >>   3 files changed, 15 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> index 5ce5f0a3d6f5..628ff89dd72f 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> @@ -1516,6 +1516,7 @@ main_r5fss0: r5fss@5c00000 { >>           ranges = <0x5c00000 0x00 0x5c00000 0x20000>, >>                <0x5d00000 0x00 0x5d00000 0x20000>; >>           power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; >> +        status = "disabled"; >>             main_r5fss0_core0: r5f@5c00000 { >>               compatible = "ti,j7200-r5f"; >> @@ -1530,6 +1531,7 @@ main_r5fss0_core0: r5f@5c00000 { >>               ti,atcm-enable = <1>; >>               ti,btcm-enable = <1>; >>               ti,loczrama = <1>; >> +            status = "disabled"; >>           }; >>             main_r5fss0_core1: r5f@5d00000 { >> @@ -1545,6 +1547,7 @@ main_r5fss0_core1: r5f@5d00000 { >>               ti,atcm-enable = <1>; >>               ti,btcm-enable = <1>; >>               ti,loczrama = <1>; >> +            status = "disabled"; >>           }; >>       }; >>   diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi >> b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi >> index 56ab144fea07..692c4745040e 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi >> @@ -612,6 +612,7 @@ mcu_r5fss0: r5fss@41000000 { >>           ranges = <0x41000000 0x00 0x41000000 0x20000>, >>                <0x41400000 0x00 0x41400000 0x20000>; >>           power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; >> +        status = "disabled"; > > Please leave boot critical fw as is. The nodes that are disabled here, are enabled back in the board level files. So, it has no effective change on the boards. > > Here are my suggestions > >  create one boot-critical-fw-dtsi for mcu_r5fss0 , include this fw > files in all boards. That is the plan for a future series :) Thanks, Beleswar > > other IPC optional firmware can reside in one dtsi or dtso, > > >> [..]