From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53334524F; Sat, 29 Mar 2025 05:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743224706; cv=none; b=YciSE9XbQDw0NYwFO6HlgBMW6by+gGiPuWFM1NYV9MfYfi77vwZzb/NEksDbJeA8R0phVTZe7ELwFxupM8kkI+VAyC8Z3wF3DWgyrOyI7NaRZVj4cSv3iK+69/lKHtJFvOGENrLxAFi3BlR5r8znLhx0VFng/1HNysvkvWEygBM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743224706; c=relaxed/simple; bh=465wNPNn0OBjQesUwHOaBKBTvwAHWe6mU+iLD4taErE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=k7EGZrD/uNE/+voaatglSnqCNh0Z52q5PIxGBs6EiiLvF6kNZKdgIjOGFYIz/3f4PBlEVZODUfYJcsCdull8rPpDttRvUJIXYv0MPLsTZpx9bqNzWV/WdGgHKK0MwaDaVOD8MlVu2iGdT7g0+PQmFo2VYEY07d0sIZPwnaigUQc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KCMUt+cX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KCMUt+cX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B891C4CEE2; Sat, 29 Mar 2025 05:05:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743224705; bh=465wNPNn0OBjQesUwHOaBKBTvwAHWe6mU+iLD4taErE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KCMUt+cXnPDQ5ok3ULfm3MY2ap7AqYTpdNlZRDUMywp+fLtr3hqfj9iTDDo4ztjQg IYt7U/jfjvdQLmPXO8BGw90Nw78D0M9Yv4QLp7b4GRDhswWpkYpwwMqVQWd4q+3JHg 35nwTOJMPwDXLRdCtI0AKeCeOmSIbgnOKtPyNUQQK8KswtczgQuU0uhmlS3FVZ3vEt 2V4xUxNOB6mzC7Qzgc7yRfRmC9CCSv6dK0nDZFQRWRgH2IyR/llwIfHfQQqoTvsyzS 9XGQvWFguAdnxFW0l1a+D0zYEgc6HFNGMb8yTLI+bz9+pO0ORsWNVIoXg+8FR0/Kaj ig3xvKcCAK5CA== Message-ID: Date: Sat, 29 Mar 2025 06:04:59 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: watchdog: Add NXP Software Watchdog Timer To: Daniel Lezcano , wim@linux-watchdog.org Cc: linux@roeck-us.net, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, S32@nxp.com, Ghennadi Procopciuc , Thomas Fossati , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" References: <20250328151516.2219971-1-daniel.lezcano@linaro.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 28/03/2025 16:15, Daniel Lezcano wrote: > +description: > + The System Timer Module supports commonly required system and > + application software timing functions. STM includes a 32-bit > + count-up timer and four 32-bit compare channels with a separate > + interrupt source for each channel. The timer is driven by the STM > + > +allOf: > + - $ref: watchdog.yaml# > + > +properties: > + compatible: > + enum: > + - nxp,s32g-wdt This wasn't tested, so limited review - this also has wrong compatible, There is no such soc as s32g in the kernel. If that's a new soc, come with proper top-level bindings and some explanation, because I am sure previously we talked with NXP that this is not s32g but something else. Best regards, Krzysztof