From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philippe Schenker Subject: Re: [PATCH 1/3] regulator: fixed: add possibility to enable by clock Date: Tue, 10 Sep 2019 06:08:59 +0000 Message-ID: References: <20190903080336.32288-1-philippe.schenker@toradex.com> <20190903080336.32288-2-philippe.schenker@toradex.com> <20190905180615.GG4053@sirena.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190905180615.GG4053@sirena.co.uk> Content-Language: en-US Content-ID: Sender: linux-kernel-owner@vger.kernel.org To: "broonie@kernel.org" Cc: Max Krummenacher , Marcel Ziswiler , Luka Pivk , "s.hauer@pengutronix.de" , "devicetree@vger.kernel.org" , "mark.rutland@arm.com" , "linux-kernel@vger.kernel.org" , Stefan Agner , "shawnguo@kernel.org" , "lgirdwood@gmail.com" , "robh+dt@kernel.org" List-Id: devicetree@vger.kernel.org T24gVGh1LCAyMDE5LTA5LTA1IGF0IDE5OjA2ICswMTAwLCBNYXJrIEJyb3duIHdyb3RlOg0KPiBP biBUdWUsIFNlcCAwMywgMjAxOSBhdCAwODowMzo0NkFNICswMDAwLCBQaGlsaXBwZSBTY2hlbmtl ciB3cm90ZToNCj4gPiBUaGlzIGNvbW1pdCBhZGRzIHRoZSBwb3NzaWJpbGl0eSB0byBjaG9vc2Ug dGhlIGNvbXBhdGlibGUNCj4gPiAicmVndWxhdG9yLWZpeGVkLWNsb2NrIiBpbiBkZXZpY2V0cmVl Lg0KPiA+IA0KPiA+IFRoaXMgaXMgYSBzcGVjaWFsIHJlZ3VsYXRvci1maXhlZCB0aGF0IGhhcyB0 byBoYXZlIGEgY2xvY2ssIGZyb20NCj4gPiB3aGljaA0KPiA+IHRoZSByZWd1bGF0b3IgZ2V0cyBz d2l0Y2hlZCBvbiBhbmQgb2ZmLg0KPiANCj4gVGhpcyBzZWVtcyBjb25jZXB0dWFsbHkgZmluZS4g IE1pbm9yIGlzc3VlcyB0aG91Z2g6DQoNClRoYW5rcyBmb3IgeW91ciBjb21tZW50cyBhbmQgSSdt IGdsYWQgeW91IGxpa2UgaXQhIEkgd2lsbCBzZW5kIGEgdjINCnNob3J0bHksIGFsc28gd2l0aCBS b2IncyBmaXhlcyBpbi4gQ2FuIEkgZXhwZWN0IGl0IHRvIGJlIHB1bGxlZCBmb3IgNS40Pw0KDQpC ZXN0IHJlZ2FyZHMsDQpQaGlsaXBwZQ0KDQo+IA0KPiA+ICtzdGF0aWMgaW50IHJlZ19jbG9ja19p c19lbmFibGVkKHN0cnVjdCByZWd1bGF0b3JfZGV2ICpyZGV2KQ0KPiA+ICt7DQo+ID4gKwlzdHJ1 Y3QgZml4ZWRfdm9sdGFnZV9kYXRhICpwcml2ID0gcmRldl9nZXRfZHJ2ZGF0YShyZGV2KTsNCj4g PiArDQo+ID4gKwlpZiAocHJpdi0+Y2xrX2VuYWJsZV9jb3VudGVyID4gMCkNCj4gPiArCQlyZXR1 cm4gMTsNCj4gPiArDQo+ID4gKwlyZXR1cm4gMDsNCj4gPiArfQ0KPiANCj4gVGhpcyBjb3VsZCBq dXN0IGJlIHJldHVybiBwcml2LT5jbGtfZW5hYmxlX2NvdW50ZXIgPiAwIC0gaWRlYWxseSB0aGUN Cj4gY2xvY2sgQVBJIHdvdWxkIGxldCB1cyBxdWVyeSBpZiB0aGUgY2xvY2sgaXMgZW5hYmxlZCBi dXQgdGhhdCBtaWdodCBiZQ0KPiBhDQo+IGJpdCBjb25mdXNlZCBhbnl3YXkgZ2l2ZW4gdGhhdCBp dCdzIHBvc3NpYmx5IHNoYXJlZC4NCg==