From: Konrad Dybcio <konradybcio@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>,
manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
kishon@kernel.org, robh@kernel.org, andersson@kernel.org,
konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org,
quic_msarkar@quicinc.com, quic_devipriy@quicinc.com
Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org,
neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 3/5] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3
Date: Tue, 17 Sep 2024 01:29:58 +0200 [thread overview]
Message-ID: <c4696a9d-e3f2-4ff5-8323-84f75f2f1a68@kernel.org> (raw)
In-Reply-To: <20240913083724.1217691-4-quic_qianyu@quicinc.com>
On 13.09.2024 10:37 AM, Qiang Yu wrote:
> Currently driver supports only x4 lane based functionality using tx/rx and
> tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3,
> PCIe3 related QMP PHY provides additional programming which are available
> as txz and rxz based register set. Hence adds txz and rxz based registers
> usage and programming sequences. Phy register setting for txz and rxz will
> be applied to all 8 lanes. Some lanes may have different settings on
> several registers than txz/rxz, these registers should be programmed after
> txz/rxz programming sequences completing.
>
> Besides, x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8.
> Add the new register offsets in a dedicated header file.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Konrad
next prev parent reply other threads:[~2024-09-16 23:30 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-13 8:37 [PATCH v2 0/5] Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-13 8:37 ` [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-09-13 13:37 ` Manivannan Sadhasivam
2024-09-19 13:47 ` Qiang Yu
2024-09-16 15:15 ` Krzysztof Kozlowski
2024-09-19 14:03 ` Qiang Yu
2024-09-19 15:37 ` Konrad Dybcio
2024-09-20 11:22 ` Krzysztof Kozlowski
2024-09-13 8:37 ` [PATCH v2 2/5] dt-bindings: PCI: qcom: Add OPP table for X1E80100 Qiang Yu
2024-09-13 12:30 ` Dmitry Baryshkov
2024-09-13 13:36 ` Manivannan Sadhasivam
2024-09-16 15:20 ` Krzysztof Kozlowski
2024-09-16 15:20 ` Krzysztof Kozlowski
2024-09-13 8:37 ` [PATCH v2 3/5] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-09-13 12:28 ` Dmitry Baryshkov
2024-09-16 23:29 ` Konrad Dybcio [this message]
2024-09-13 8:37 ` [PATCH v2 4/5] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-09-13 8:37 ` [PATCH v2 5/5] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-13 12:35 ` Dmitry Baryshkov
2024-09-13 13:57 ` Manivannan Sadhasivam
2024-09-19 14:05 ` Qiang Yu
2024-09-14 3:59 ` [PATCH v2 0/5] " Krishna Chaitanya Chundru
2024-09-19 14:14 ` Qiang Yu
2024-09-22 17:09 ` Manivannan Sadhasivam
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