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Thu, 16 Oct 2025 02:08:21 -0700 (PDT) Message-ID: Subject: Re: [PATCH 3/6] spi: add multi_bus_mode field to struct spi_transfer From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Date: Thu, 16 Oct 2025 10:08:53 +0100 In-Reply-To: References: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> <20251014-spi-add-multi-bus-support-v1-3-2098c12d6f5f@baylibre.com> <9269eadc1ea593e5bc8f5cad8061b48220f4d2b2.camel@gmail.com> <409ad505-8846-443e-8d71-baca3c9aef21@sirena.org.uk> <12db0930458ceb596010655736b0a67a0ad0ae53.camel@gmail.com> <8c7bf62a-c5dc-4e4d-8059-8abea15ba94e@sirena.org.uk> <9024f05854dcc3cc59345c0a3de900f57c4730d9.camel@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2025-10-15 at 13:38 -0500, David Lechner wrote: > On 10/15/25 11:43 AM, Nuno S=C3=A1 wrote: > > On Wed, 2025-10-15 at 11:15 -0500, David Lechner wrote: > > > On 10/15/25 10:18 AM, Mark Brown wrote: > > > > On Wed, Oct 15, 2025 at 03:43:09PM +0100, Nuno S=C3=A1 wrote: > > > > > On Wed, 2025-10-15 at 13:01 +0100, Mark Brown wrote: > > > > > > On Wed, Oct 15, 2025 at 11:16:01AM +0100, Nuno S=C3=A1 wrote: > > > > > > > On Tue, 2025-10-14 at 17:02 -0500, David Lechner wrote: > > > >=20 > > > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 controller=C2=A0= =C2=A0=C2=A0 < data bits <=C2=A0=C2=A0=C2=A0=C2=A0 peripheral > > > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ----------=C2=A0= =C2=A0 ----------------=C2=A0=C2=A0 ---------- > > > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 SDI 0=C2=A0=C2=A0=C2=A0 0-0-0-1-0-0-0-1=C2=A0=C2=A0=C2=A0 SDO 0 > > > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 SDI 1=C2=A0=C2=A0=C2=A0 1-0-0-0-1-0-0-0=C2=A0=C2=A0=C2=A0 SDO 1 > > > >=20 > > > > > > > Out of curiosity, how does this work for devices like AD4030 = where > > > > > > > the same > > > > > > > word > > >=20 > > > The AD4030 is just one channel, so doesn't do interleaving. But you > > > probably > > > meant AD4630 when it is wired up with only 1 SDO line. That line has = to be > > > shared > > > by both of the simultaneous converters so it alternates between sendi= ng > > > one bit > > > from each word. This patch series doesn't address that case. But this > > > series will > > > work for the AD4630 when it has 2 SDO lines wired up. > > >=20 > >=20 > > Hmm I didn't even remembered that one. But what I meant with interleave= d was > > having > > the same data word spread through multiple SDO lines (one bit per line) > > which is what > > (also) happens with the devices I mentioned. And since you mentioned ".= ..two > > different data words at the same time, one on each bus...", I raised th= e > > question. >=20 > Ah, yes, I know what you are talking about now. I didn't mention that use= case > in > the cover letter because I didn't want to confuse things. But actually th= e > AD4630 > can have 8 SDO lines, 4 per each data bus/ADC channel. The groups of 4 ac= t > like a > quad SPI where 4 bits of one data word are sent at the same time. Those 4 > lines are > considered one "bus" since they are all connected to the same serialzer t= hat > combines > the bits into a single word. We already have support for this sort of thi= ng in > Linux. > And sure, we could mix the two together. So a SPI transfer might look lik= e: >=20 > struct spi_transfer example =3D { > rx_buf =3D rx_buf; > len =3D 4; /* 2 x 16-bit words */ > rx_nbits =3D 4; /* each bus is quad SPI */ > multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE; /* 2 data buses */ > bits_per_word =3D 16; > }; >=20 > This would result in a transfer that reads two 16-bit words in 4 SCLK cyc= les. >=20 > And the .dts would look like: >=20 > spi { > adc@0 { > compatible =3D "adi,ad4630-16"; > reg =3D <0>; > ... > spi-rx-bus-width =3D <4>; > spi-buses =3D <2>; > ... > }; > }; Yes, it makes sense! I guess the above is what Mark meant in the first plac= e. >=20 > The AXI SPI Engine doesn't know how to do the quad SPI part yet though, s= o > it isn't something we could implement right now. >=20 > If we tried to do it with spi-buses =3D <8>; then we would end up with th= e > "interleaved" bits (or nibbles depending on the wiring) that requires the > extra IP block to sort out when using SPI offloading. Technically, we cou= ld I think that extra block already exists today. I was thinking the idea was = just: // the case where we just have one channel with eg: 32 bits words (eg: test patterns)=20 struct spi_transfer example =3D { rx_buf =3D rx_buf; len =3D 1; /* 1 32bit words */ /* 4 lanes which is actually quadspi */ multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE;=20 }; I still did not looked at how the stripe mode is implemented in the hdl IP = but maybe the above would work as we get 8 bits per lane and we do have the dat= a reorder IP (or at least used to have) after the offload engine.=C2=A0 That said, I do see now the above is not the intended usecase for this seri= es and even if it works we kind of have to hack the xfer len to 1 which does n= ot reflect reality. > make it work, but it would require a bunch of extra hardware description = that > the driver would have to interpret in order to correctly format the struc= t > spi_transfer. I was hoping we could avoid that and just teach the SPI Eng= ine > how to do dual/quad SPI like other SPI controllers. Agreed! - Nuno S=C3=A1 > > > > >=20