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Thu, 16 Oct 2025 11:37:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFopTCf5Sn+ugIQazeLjzMKZ4AaB+rCH/4DczDVKRWHWy44mdCx7hroKoHEE+1V8Q7zPobuqA== X-Received: by 2002:a17:902:d584:b0:275:f156:965c with SMTP id d9443c01a7336-290cb65b61dmr10962635ad.52.1760639829227; Thu, 16 Oct 2025 11:37:09 -0700 (PDT) Received: from [192.168.0.167] ([49.205.248.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-290c5c7d305sm11890295ad.70.2025.10.16.11.37.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Oct 2025 11:37:08 -0700 (PDT) Message-ID: Date: Fri, 17 Oct 2025 00:07:02 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file Content-Language: en-US To: Dmitry Baryshkov Cc: Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vishnu Reddy References: <20250925-knp_video-v1-0-e323c0b3c0cd@oss.qualcomm.com> <20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com> From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: PYnh4797fa1hDTQAtgz_qsup-gIPRqpL X-Proofpoint-ORIG-GUID: PYnh4797fa1hDTQAtgz_qsup-gIPRqpL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAxNyBTYWx0ZWRfXwNDoYiwXOTQL MKFM9vRjSxZJXGOaxt2nwTcuGi3pnmRqLSyELdZCyzeQ5FpHQXfOAi23DGRMuC9IkSq/qEzER+T 0yUK+O/Bxy7zQmGUGY5cRryY8AG49qlTEYyaaRDe0Q4iJxzD83iglIjJI9ZbIpua5ft2qx/mItT lMGZFghtTLGq+nfj51vjZHDQ7ceGGcWoEQsv2WGZwjB8S/vmnBMj2vCNvn3pqcuHnfQ14CWTiu1 H1nNt4OUS/x9lvajjVMZDHbIjpF45wGd1d/e2zJ2nqEtPEfzFVFf6NNGnHhi0vZOErBSricET5t LA02CmdWtxE5sDjqK3N9aKbQfpZJchyDPiY4yRnKf4nNaI+DIt8m1xMT3d7g4bFNnXqiIh5rZXZ tKf/LpwEYv2kv355kS90Wiq1mkCK7Q== X-Authority-Analysis: v=2.4 cv=JLw2csKb c=1 sm=1 tr=0 ts=68f13b57 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=LqmlnLjRnrQCSl2bsDkM0Q==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Da5OPgB5uXQvAvJx2EkA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110017 On 10/16/2025 7:17 PM, Dmitry Baryshkov wrote: >> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h >> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..6474f561c8dc29d1975bb44792595d86f16b6cff 100644 >> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h >> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h >> @@ -9,9 +9,38 @@ >> #define VCODEC_BASE_OFFS 0x00000000 >> #define CPU_BASE_OFFS 0x000A0000 >> #define WRAPPER_BASE_OFFS 0x000B0000 >> +#define AON_BASE_OFFS 0x000E0000 >> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 >> +#define AON_MVP_NOC_RESET 0x0001F000 >> >> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS) >> >> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) >> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) >> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) >> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) >> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) >> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) >> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) >> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) >> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) >> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) >> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) >> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) >> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) >> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) >> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > Registers here got totally unsorted (they were in the original source > file). Seeing this makes me sad. > Sure, i will be improving this part in v2. >> + >> +#define CORE_BRIDGE_SW_RESET BIT(0) >> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) >> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) >> +#define MSK_CORE_POWER_ON BIT(1) >> +#define CTL_AXI_CLK_HALT BIT(0) >> +#define CTL_CLK_HALT BIT(1) >> +#define REQ_POWER_DOWN_PREP BIT(0) >> +#define RESET_HIGH BIT(0) >> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ >> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ >> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > Ugh. This mixed all the bits, loosing connection between the register > and the corresponding bits. I'm going to pick up this patch into the > sc7280 series and I will improve it there, keeping the link between > registers and bit fields. > Ok, not updating this part in the next revision of my series. Do you mean something like #define CORE_BRIDGE_SW_RESET_BIT0 BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE_BIT1 BIT(1) Regards, Vikash