[PATCH v3 4/5] i2c: tegra: Add support for SW mutex register

Kartik Rajput
2025-06-09T09:34:59Z

Add support for SW mutex register introduced in Tegra264 to provide
an option to share the interface between multiple firmwares and/or
VMs.

However, the hardware does not ensure any protection based on the
values. The driver/firmware should honor the peer who already holds
the mutex.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
---
v2 -> v3:
* Update tegra_i2c_mutex_trylock and tegra_i2c_mutex_unlock to
use readl and writel APIs instead of i2c_readl and i2c_writel
which use relaxed APIs.
* Use dev_warn instead of WARN_ON if mutex lock/unlock fails.
v1 -> v2:
* Fixed typos.
* Fix tegra_i2c_mutex_lock() logic.
* Add a timeout in tegra_i2c_mutex_lock() instead of polling for
mutex indefinitely.
---
drivers/i2c/busses/i2c-tegra.c | 137 +++++++++++++++++++++++++++++----
1 file changed, 122 insertions(+), 15 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index d0b6aa013c96..dae59e9e993b 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -137,6 +137,14 @@

#define I2C_MASTER_RESET_CNTRL 0x0a8

+#define I2C_SW_MUTEX 0x0ec
+#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0)
+#define I2C_SW_MUTEX_GRANT GENMASK(7, 4)
+#define I2C_SW_MUTEX_ID 9
+
+/* SW mutex acquire timeout value in milliseconds. */
+#define I2C_SW_MUTEX_TIMEOUT 25
+
/* configuration load timeout in microseconds */
#define I2C_CONFIG_LOAD_TIMEOUT 1000000

@@ -210,6 +218,7 @@ enum msg_end_type {
* @has_interface_timing_reg: Has interface timing register to program the tuned
* timing settings.
* @has_hs_mode_support: Has support for high speed (HS) mode transfers.
+ * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
*/
struct tegra_i2c_hw_feature {
bool has_continue_xfer_support;
@@ -237,6 +246,7 @@ struct tegra_i2c_hw_feature {
u32 setup_hold_time_hs_mode;
bool has_interface_timing_reg;
bool has_hs_mode_support;
+ bool has_mutex;
};

/**
@@ -380,6 +390,108 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
}

+static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
+ u32 reg, u32 mask, u32 delay_us,
+ u32 timeout_us)
+{
+ void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
+ u32 val;
+
+ if (!i2c_dev->atomic_mode)
+ return readl_relaxed_poll_timeout(addr, val, !(val & mask),
+ delay_us, timeout_us);
+
+ return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
+ delay_us, timeout_us);
+}
+
+static int tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
+{
+ unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+ u32 val, id;
+
+ val = readl(i2c_dev->base + reg);
+ id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+ if (id != 0 && id != I2C_SW_MUTEX_ID)
+ return 0;
+
+ val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID);
+ writel(val, i2c_dev->base + reg);
+
+ val = readl(i2c_dev->base + reg);
+ id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+
+ if (id != I2C_SW_MUTEX_ID)
+ return 0;
+
+ return 1;
+}
+
+static void tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev)
+{
+ unsigned int num_retries = I2C_SW_MUTEX_TIMEOUT;
+
+ /* Poll until mutex is acquired or timeout. */
+ while (--num_retries && !tegra_i2c_mutex_trylock(i2c_dev))
+ usleep_range(1000, 2000);
+
+ if (!num_retries)
+ dev_warn(i2c_dev->dev, "timeout while acquiring mutex, proceeding anyway\n");
+}
+
+static void tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev)
+{
+ unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+ u32 val, id;
+
+ val = readl(i2c_dev->base + reg);
+ id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+
+ if (id != I2C_SW_MUTEX_ID) {
+ dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n", id);
+ return;
+ }
+
+ writel(0, i2c_dev->base + reg);
+}
+
+static void tegra_i2c_bus_lock(struct i2c_adapter *adapter,
+ unsigned int flags)
+{
+ struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
+
+ rt_mutex_lock_nested(&adapter->bus_lock, i2c_adapter_depth(adapter));
+ tegra_i2c_mutex_lock(i2c_dev);
+}
+
+static int tegra_i2c_bus_trylock(struct i2c_adapter *adapter,
+ unsigned int flags)
+{
+ struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
+ int ret;
+
+ ret = rt_mutex_trylock(&adapter->bus_lock);
+ if (ret)
+ ret = tegra_i2c_mutex_trylock(i2c_dev);
+
+ return ret;
+}
+
+static void tegra_i2c_bus_unlock(struct i2c_adapter *adapter,
+ unsigned int flags)
+{
+ struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
+
+ tegra_i2c_mutex_unlock(i2c_dev);
+ rt_mutex_unlock(&adapter->bus_lock);
+}
+
+static const struct i2c_lock_operations tegra_i2c_lock_ops = {
+ .lock_bus = tegra_i2c_bus_lock,
+ .trylock_bus = tegra_i2c_bus_trylock,
+ .unlock_bus = tegra_i2c_bus_unlock,
+};
+
static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
{
u32 int_mask;
@@ -558,21 +670,6 @@ static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
}

-static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
- u32 reg, u32 mask, u32 delay_us,
- u32 timeout_us)
-{
- void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
- u32 val;
-
- if (!i2c_dev->atomic_mode)
- return readl_relaxed_poll_timeout(addr, val, !(val & mask),
- delay_us, timeout_us);
-
- return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
- delay_us, timeout_us);
-}
-
static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
{
u32 mask, val, offset;
@@ -1515,6 +1612,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
.setup_hold_time_fast_fast_plus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .has_mutex = false,
};

static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
@@ -1540,6 +1638,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
.setup_hold_time_fast_fast_plus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .has_mutex = false,
};

static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
@@ -1565,6 +1664,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
.setup_hold_time_fast_fast_plus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .has_mutex = false,
};

static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
@@ -1590,6 +1690,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
.setup_hold_time_fast_fast_plus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = true,
+ .has_mutex = false,
};

static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
@@ -1615,6 +1716,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
.setup_hold_time_fast_fast_plus_mode = 0,
.setup_hold_time_hs_mode = 0,
.has_interface_timing_reg = true,
+ .has_mutex = false,
};

static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
@@ -1640,6 +1742,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
.setup_hold_time_fast_fast_plus_mode = 0,
.setup_hold_time_hs_mode = 0,
.has_interface_timing_reg = true,
+ .has_mutex = false,
};

static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
@@ -1668,6 +1771,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
.setup_hold_time_hs_mode = 0x090909,
.has_interface_timing_reg = true,
.has_hs_mode_support = true,
+ .has_mutex = false,
};

static const struct of_device_id tegra_i2c_of_match[] = {
@@ -1871,6 +1975,9 @@ static int tegra_i2c_probe(struct platform_device *pdev)
i2c_dev->adapter.nr = pdev->id;
ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev));

+ if (i2c_dev->hw->has_mutex)
+ i2c_dev->adapter.lock_ops = &tegra_i2c_lock_ops;
+
if (i2c_dev->hw->supports_bus_clear)
i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;

--
2.43.0