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[83.9.29.96]) by smtp.gmail.com with ESMTPSA id m12-20020a19520c000000b004eb12850c40sm1207281lfb.14.2023.06.05.11.21.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Jun 2023 11:21:41 -0700 (PDT) Message-ID: Date: Mon, 5 Jun 2023 20:21:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v2 10/10] arm64: dts: qcom: Add the support of cpufreq on SDX75 Content-Language: en-US To: Rohit Agarwal , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, tglx@linutronix.de, maz@kernel.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, mani@kernel.org, robimarko@gmail.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev References: <1685982557-28326-1-git-send-email-quic_rohiagar@quicinc.com> <1685982557-28326-11-git-send-email-quic_rohiagar@quicinc.com> From: Konrad Dybcio In-Reply-To: <1685982557-28326-11-git-send-email-quic_rohiagar@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 5.06.2023 18:29, Rohit Agarwal wrote: > Add the support of cpufreq to enable the cpufreq scaling > on SDX75 SoC. Also add CPU specific information to build > energy model for EAS. > > Signed-off-by: Rohit Agarwal > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index 47170ae..e1887a4 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -47,10 +47,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD0>; > power-domain-names = "psci"; > next-level-cache = <&L2_0>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_0: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -64,10 +68,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD1>; > power-domain-names = "psci"; > next-level-cache = <&L2_100>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_100: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -78,10 +86,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD2>; > power-domain-names = "psci"; > next-level-cache = <&L2_200>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_200: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -92,10 +104,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD3>; > power-domain-names = "psci"; > next-level-cache = <&L2_300>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; That sounds a bit bogus.. Thinking about it, it sounds bogus on most platforms we have support for! I guess SM8250 big cores aren't *really* equally as powerful.. > + dynamic-power-coefficient = <100>; > L2_300: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -605,6 +621,20 @@ > }; > > }; > + > + cpufreq_hw: cpufreq@17d91000 { > + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; > + reg = <0 0x17d91000 0 0x1000>; You used 0x0 instead of 0 everywhere else, please do so here as well to keep things consistent. With that: Reviewed-by: Konrad Dybcio Konrad > + reg-names = "freq-domain0"; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GPLL0>; > + clock-names = "xo", > + "alternate"; > + interrupts = ; > + interrupt-names = "dcvsh-irq-0"; > + #freq-domain-cells = <1>; > + #clock-cells = <1>; > + }; > }; > > timer {